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[HeterogeneousDwarf] Thread-focus vector registers in AsmPrinter (llvm#773)
2 parents 8753947 + 9f9a725 commit 6d27f9d

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7 files changed

+56
-16
lines changed

7 files changed

+56
-16
lines changed

‎llvm/include/llvm/CodeGen/TargetRegisterInfo.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1063,6 +1063,14 @@ class TargetRegisterInfo : public MCRegisterInfo {
10631063
prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags,
10641064
const StackOffset &Offset) const;
10651065

1066+
/// If the register corresponding to DwarfReg is a vector register that holds
1067+
/// a per-thread value in each lane, return the size in bytes of the lane.
1068+
/// Otherwise return nullopt.
1069+
virtual std::optional<unsigned> getDwarfRegLaneSize(int64_t DwarfReg,
1070+
bool isEH) const {
1071+
return std::nullopt;
1072+
}
1073+
10661074
/// Spill the register so it can be used by the register scavenger.
10671075
/// Return true if the register was spilled, false otherwise.
10681076
/// If this function does not spill the register, the scavenger

‎llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp

Lines changed: 15 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -945,7 +945,7 @@ std::optional<NewOpResult> DwarfExpression::traverse(DIOp::Arg Arg,
945945

946946
if (Entry.isLocation()) {
947947
assert(DwarfRegs.empty() && "unconsumed registers?");
948-
if (!addMachineReg(*TRI, Entry.getLoc().getReg())) {
948+
if (!TRI || !addMachineReg(*TRI, Entry.getLoc().getReg())) {
949949
DwarfRegs.clear();
950950
return std::nullopt;
951951
}
@@ -962,8 +962,19 @@ std::optional<NewOpResult> DwarfExpression::traverse(DIOp::Arg Arg,
962962
SubRegOffset /= 8;
963963
SubRegSize /= 8;
964964

965+
auto focusThreadIfRequired = [this](int64_t DwarfRegNo) {
966+
// FIXME: This should be represented in the DIExpression.
967+
if (auto LaneSize = TRI->getDwarfRegLaneSize(DwarfRegNo, false)) {
968+
emitUserOp(dwarf::DW_OP_LLVM_USER_push_lane);
969+
emitConstu(*LaneSize);
970+
emitOp(dwarf::DW_OP_mul);
971+
emitUserOp(dwarf::DW_OP_LLVM_USER_offset);
972+
}
973+
};
974+
965975
if (Regs.size() == 1) {
966976
addReg(Regs[0].DwarfRegNo, Regs[0].Comment);
977+
focusThreadIfRequired(Regs[0].DwarfRegNo);
967978

968979
if (SubRegOffset) {
969980
emitUserOp(dwarf::DW_OP_LLVM_USER_offset_uconst);
@@ -988,13 +999,13 @@ std::optional<NewOpResult> DwarfExpression::traverse(DIOp::Arg Arg,
988999
if (IsFragment)
9891000
emitOp(dwarf::DW_OP_lit0);
9901001

991-
unsigned RegSize = 0;
9921002
for (auto &Reg : Regs) {
9931003
if (Reg.SubRegSize % 8)
9941004
return std::nullopt;
995-
RegSize += Reg.SubRegSize;
996-
if (Reg.DwarfRegNo >= 0)
1005+
if (Reg.DwarfRegNo >= 0) {
9971006
addReg(Reg.DwarfRegNo, Reg.Comment);
1007+
focusThreadIfRequired(Regs[0].DwarfRegNo);
1008+
}
9981009
emitOp(dwarf::DW_OP_piece);
9991010
emitUnsigned(Reg.SubRegSize / 8);
10001011
}

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -967,6 +967,16 @@ bool SIRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
967967
SIInstrFlags::FlatScratch);
968968
}
969969

970+
std::optional<unsigned> SIRegisterInfo::getDwarfRegLaneSize(int64_t DwarfReg,
971+
bool IsEH) const {
972+
if (std::optional<MCRegister> Reg = getLLVMRegNum(DwarfReg, IsEH)) {
973+
const TargetRegisterClass *RC = getPhysRegBaseClass(*Reg);
974+
if (RC == &AMDGPU::VGPR_32RegClass || RC == &AMDGPU::AGPR_32RegClass)
975+
return 4;
976+
}
977+
return std::nullopt;
978+
}
979+
970980
const TargetRegisterClass *SIRegisterInfo::getPointerRegClass(
971981
const MachineFunction &MF, unsigned Kind) const {
972982
// This is inaccurate. It depends on the instruction and address space. The

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -143,6 +143,9 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
143143
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
144144
int64_t Offset) const override;
145145

146+
std::optional<unsigned> getDwarfRegLaneSize(int64_t DwarfReg,
147+
bool isEH) const override;
148+
146149
const TargetRegisterClass *getPointerRegClass(
147150
const MachineFunction &MF, unsigned Kind = 0) const override;
148151

‎llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-diexpression-args.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ define amdgpu_kernel void @int64_k(i64 %a) !dbg !31 {
2525
; CHECK-LABEL: DW_AT_name ("as1_ptr")
2626
define void @as1_ptr(ptr addrspace(1) %ptr) !dbg !16 {
2727
; CHECK: DW_AT_location
28-
; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_piece 0x4, DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_piece 0x4)
28+
; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4)
2929
tail call void @llvm.dbg.value(metadata ptr addrspace(1) %ptr, metadata !17, metadata !DIExpression(DIOpArg(0, ptr addrspace(1)))), !dbg !20
3030
store ptr addrspace(1) %ptr, ptr @glob_ptr, align 8, !dbg !20
3131
ret void, !dbg !20
@@ -34,15 +34,15 @@ define void @as1_ptr(ptr addrspace(1) %ptr) !dbg !16 {
3434
; CHECK-LABEL: DW_AT_name ("int64")
3535
define void @int64(i64 %a) !dbg !21 {
3636
; CHECK: DW_AT_location
37-
; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_piece 0x4, DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_piece 0x4)
37+
; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4)
3838
tail call void @llvm.dbg.value(metadata i64 %a, metadata !22, metadata !DIExpression(DIOpArg(0, i64))), !dbg !23
3939
store i64 %a, ptr @glob_ptr, align 8, !dbg !23
4040
ret void, !dbg !24
4141
}
4242

4343
; CHECK-LABEL: DW_AT_name ("int32")
4444
define void @int32(i32 %a) !dbg !25 {
45-
; CHECK: DW_AT_location (DW_OP_regx 0x{{[0-9a-z]+}})
45+
; CHECK: DW_AT_location (DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset)
4646
tail call void @llvm.dbg.value(metadata i32 %a, metadata !26, metadata !DIExpression(DIOpArg(0, i32))), !dbg !27
4747
store i32 %a, ptr @glob_ptr, align 4, !dbg !27
4848
ret void, !dbg !27
@@ -51,7 +51,7 @@ define void @int32(i32 %a) !dbg !25 {
5151
; CHECK-LABEL: DW_AT_name ("gen_ptr")
5252
define void @gen_ptr(ptr %ptr) !dbg !28 {
5353
; CHECK: DW_AT_location
54-
; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_piece 0x4, DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_piece 0x4)
54+
; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx 0x{{[0-9a-z]+}}, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4)
5555
tail call void @llvm.dbg.value(metadata ptr %ptr, metadata !29, metadata !DIExpression(DIOpArg(0, ptr))), !dbg !30
5656
store ptr %ptr, ptr @glob_ptr, align 8, !dbg !30
5757
ret void, !dbg !30

‎llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-diexpression-subregs.mir

Lines changed: 13 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
define void @kern() #0 !dbg !9 {
88
ret void, !dbg !16
99
}
10-
attributes #0 = { convergent mustprogress noinline nounwind optnone "amdgpu-stack-objects" "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="+16-bit-insts,+ci-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst" "uniform-work-group-size"="false" }
10+
attributes #0 = { noinline optnone }
1111

1212
!llvm.dbg.cu = !{!0}
1313
!llvm.module.flags = !{!2, !3, !4, !5, !6, !7}
@@ -39,6 +39,7 @@
3939
!23 = !DILocalVariable(name: "with_frags", scope: !9, file: !1, line: 1, type: !15)
4040
!24 = !DILocalVariable(name: "sgpr", scope: !9, file: !1, line: 1, type: !14)
4141
!25 = !DILocalVariable(name: "vgpr", scope: !9, file: !1, line: 1, type: !14)
42+
!26 = !DILocalVariable(name: "vgpr_frags", scope: !9, file: !1, line: 1, type: !15)
4243

4344
...
4445
---
@@ -58,15 +59,15 @@ body: |
5859
; CHECK-NEXT: DW_AT_name ("s_s")
5960
DBG_VALUE renamable $sgpr42_sgpr43, $noreg, !19, !DIExpression(DIOpArg(0, i64)), debug-location !16
6061
61-
; CHECK: DW_AT_location (DW_OP_regx VGPR42, DW_OP_deref_size 0x2, DW_OP_stack_value)
62+
; CHECK: DW_AT_location (DW_OP_regx VGPR42, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_deref_size 0x2, DW_OP_stack_value)
6263
; CHECK-NEXT: DW_AT_name ("v_lo16")
6364
DBG_VALUE renamable $vgpr42_lo16, $noreg, !20, !DIExpression(DIOpArg(0, i16)), debug-location !16
6465
65-
; CHECK: DW_AT_location (DW_OP_regx VGPR42, DW_OP_LLVM_user DW_OP_LLVM_offset_uconst 0x2, DW_OP_deref_size 0x2, DW_OP_stack_value)
66+
; CHECK: DW_AT_location (DW_OP_regx VGPR42, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_LLVM_user DW_OP_LLVM_offset_uconst 0x2, DW_OP_deref_size 0x2, DW_OP_stack_value)
6667
; CHECK-NEXT: DW_AT_name ("v_hi16")
6768
DBG_VALUE renamable $vgpr42_hi16, $noreg, !21, !DIExpression(DIOpArg(0, i16)), debug-location !16
6869
69-
; CHECK: DW_AT_location (DW_OP_regx VGPR42, DW_OP_piece 0x4, DW_OP_regx VGPR43, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_piece_end)
70+
; CHECK: DW_AT_location (DW_OP_regx VGPR42, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx VGPR43, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_piece_end)
7071
; CHECK-NEXT: DW_AT_name ("v_v")
7172
DBG_VALUE renamable $vgpr42_vgpr43, $noreg, !22, !DIExpression(DIOpArg(0, i64)), debug-location !16
7273
@@ -81,10 +82,17 @@ body: |
8182
; CHECK-NEXT: DW_AT_name ("sgpr")
8283
DBG_VALUE $sgpr100, $noreg, !24, !DIExpression(DIOpArg(0, i32)), debug-location !16
8384
84-
; CHECK: DW_AT_location (DW_OP_regx VGPR100)
85+
; CHECK: DW_AT_location (DW_OP_regx VGPR100, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset)
8586
; CHECK-NEXT: ("vgpr")
8687
DBG_VALUE $vgpr100, $noreg, !25, !DIExpression(DIOpArg(0, i32)), debug-location !16
8788
89+
; CHECK: DW_TAG_variable
90+
; CHECK-NEXT: DW_AT_location (indexed ({{.*}}) loclist = {{.*}}:
91+
; CHECK-NEXT: [{{.*}}): DW_OP_lit0, DW_OP_regx VGPR42, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx VGPR43, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_piece_end, DW_OP_swap, DW_OP_drop, DW_OP_piece 0x4, DW_OP_lit0, DW_OP_regx VGPR44, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx VGPR45, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_LLVM_user DW_OP_LLVM_piece_end, DW_OP_swap, DW_OP_drop, DW_OP_piece 0x4)
92+
; CHECK-NEXT: DW_AT_name ("vgpr_frags")
93+
DBG_VALUE renamable $vgpr42_vgpr43, $noreg, !26, !DIExpression(DIOpArg(0, i64), DIOpFragment(0, 32)), debug-location !16
94+
DBG_VALUE renamable $vgpr44_vgpr45, $noreg, !26, !DIExpression(DIOpArg(0, i64), DIOpFragment(32, 32)), debug-location !16
95+
8896
S_ENDPGM 0, debug-location !16
8997
9098
...

‎llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-frags.mir

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -55,18 +55,18 @@ body: |
5555
5656
5757
; CHECK: DW_AT_location
58-
; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_piece 0x2, DW_OP_regx VGPR44, DW_OP_piece 0x4, DW_OP_regx VGPR45, DW_OP_piece 0x2
58+
; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_piece 0x2, DW_OP_regx VGPR44, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x4, DW_OP_regx VGPR45, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x2
5959
DBG_VALUE renamable $vgpr43, $noreg, !18, !DIExpression(DW_OP_LLVM_poisoned, DW_OP_LLVM_fragment, 0, 32), debug-location !14
6060
DBG_VALUE renamable $vgpr44, $noreg, !18, !DIExpression(DIOpArg(0, i32), DIOpFragment(16, 32)), debug-location !14
6161
DBG_VALUE renamable $vgpr45, $noreg, !18, !DIExpression(DIOpArg(0, i32), DIOpFragment(48, 16)), debug-location !14
6262
S_NOP 0, debug-location !14
6363
64-
; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx VGPR46, DW_OP_piece 0x1, DW_OP_piece 0x1, DW_OP_LLVM_user DW_OP_LLVM_undefined, DW_OP_piece 0x2, DW_OP_piece 0x2, DW_OP_regx VGPR45, DW_OP_piece 0x2
64+
; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx VGPR46, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x1, DW_OP_piece 0x1, DW_OP_LLVM_user DW_OP_LLVM_undefined, DW_OP_piece 0x2, DW_OP_piece 0x2, DW_OP_regx VGPR45, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x2
6565
DBG_VALUE renamable $vgpr46, $noreg, !18, !DIExpression(DIOpArg(0, i32), DIOpFragment(0, 8)), debug-location !15
6666
DBG_VALUE renamable $vgpr47, $noreg, !18, !DIExpression(DW_OP_LLVM_poisoned, DW_OP_LLVM_fragment, 16, 16), debug-location !15
6767
S_NOP 0, debug-location !15
6868
69-
; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx VGPR46, DW_OP_piece 0x1, DW_OP_LLVM_user DW_OP_LLVM_undefined, DW_OP_piece 0x7
69+
; CHECK-NEXT: [0x{{[0-9a-z]+}}, 0x{{[0-9a-z]+}}): DW_OP_regx VGPR46, DW_OP_LLVM_user DW_OP_LLVM_push_lane, DW_OP_lit4, DW_OP_mul, DW_OP_LLVM_user DW_OP_LLVM_offset, DW_OP_piece 0x1, DW_OP_LLVM_user DW_OP_LLVM_undefined, DW_OP_piece 0x7
7070
; CHECK-NEXT: DW_AT_name ("overlaps")
7171
DBG_VALUE renamable $vgpr48, $noreg, !18, !DIExpression(DW_OP_LLVM_poisoned, DW_OP_LLVM_fragment, 8, 56), debug-location !16
7272

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