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vangthao95Makarand Maydeo
vangthao95
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Makarand Maydeo
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[AMDGPU] Fix negative immediate offset for unbuffered smem loads (llvm#89165)
For unbuffered smem loads, it is illegal for the immediate offset to be negative if the resulting IOFFSET + (SGPR[Offset] or M0 or zero) is negative. New PR of llvm#79553. Change-Id: Ieb5681777d517fbc6ea59014af8babc9980c2b1e
1 parent 77cf9ad commit 7fe5dc8

12 files changed

+357
-104
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

Lines changed: 45 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1980,28 +1980,50 @@ bool AMDGPUDAGToDAGISel::SelectScratchSVAddr(SDNode *N, SDValue Addr,
19801980
return true;
19811981
}
19821982

1983+
// For unbuffered smem loads, it is illegal for the Immediate Offset to be
1984+
// negative if the resulting (Offset + (M0 or SOffset or zero) is negative.
1985+
// Handle the case where the Immediate Offset + SOffset is negative.
1986+
bool AMDGPUDAGToDAGISel::isSOffsetLegalWithImmOffset(SDValue *SOffset,
1987+
bool Imm32Only,
1988+
bool IsBuffer,
1989+
int64_t ImmOffset) const {
1990+
if (!IsBuffer && !Imm32Only && ImmOffset < 0 &&
1991+
AMDGPU::hasSMRDSignedImmOffset(*Subtarget)) {
1992+
KnownBits SKnown = CurDAG->computeKnownBits(*SOffset);
1993+
if (ImmOffset + SKnown.getMinValue().getSExtValue() < 0)
1994+
return false;
1995+
}
1996+
1997+
return true;
1998+
}
1999+
19832000
// Match an immediate (if Offset is not null) or an SGPR (if SOffset is
19842001
// not null) offset. If Imm32Only is true, match only 32-bit immediate
19852002
// offsets available on CI.
19862003
bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
19872004
SDValue *SOffset, SDValue *Offset,
1988-
bool Imm32Only, bool IsBuffer) const {
2005+
bool Imm32Only, bool IsBuffer,
2006+
bool HasSOffset,
2007+
int64_t ImmOffset) const {
19892008
assert((!SOffset || !Offset) &&
19902009
"Cannot match both soffset and offset at the same time!");
19912010

19922011
ConstantSDNode *C = dyn_cast<ConstantSDNode>(ByteOffsetNode);
19932012
if (!C) {
19942013
if (!SOffset)
19952014
return false;
2015+
19962016
if (ByteOffsetNode.getValueType().isScalarInteger() &&
19972017
ByteOffsetNode.getValueType().getSizeInBits() == 32) {
19982018
*SOffset = ByteOffsetNode;
1999-
return true;
2019+
return isSOffsetLegalWithImmOffset(SOffset, Imm32Only, IsBuffer,
2020+
ImmOffset);
20002021
}
20012022
if (ByteOffsetNode.getOpcode() == ISD::ZERO_EXTEND) {
20022023
if (ByteOffsetNode.getOperand(0).getValueType().getSizeInBits() == 32) {
20032024
*SOffset = ByteOffsetNode.getOperand(0);
2004-
return true;
2025+
return isSOffsetLegalWithImmOffset(SOffset, Imm32Only, IsBuffer,
2026+
ImmOffset);
20052027
}
20062028
}
20072029
return false;
@@ -2012,8 +2034,8 @@ bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
20122034
// GFX9 and GFX10 have signed byte immediate offsets. The immediate
20132035
// offset for S_BUFFER instructions is unsigned.
20142036
int64_t ByteOffset = IsBuffer ? C->getZExtValue() : C->getSExtValue();
2015-
std::optional<int64_t> EncodedOffset =
2016-
AMDGPU::getSMRDEncodedOffset(*Subtarget, ByteOffset, IsBuffer);
2037+
std::optional<int64_t> EncodedOffset = AMDGPU::getSMRDEncodedOffset(
2038+
*Subtarget, ByteOffset, IsBuffer, HasSOffset);
20172039
if (EncodedOffset && Offset && !Imm32Only) {
20182040
*Offset = CurDAG->getTargetConstant(*EncodedOffset, SL, MVT::i32);
20192041
return true;
@@ -2072,13 +2094,22 @@ SDValue AMDGPUDAGToDAGISel::Expand32BitAddress(SDValue Addr) const {
20722094
// true, match only 32-bit immediate offsets available on CI.
20732095
bool AMDGPUDAGToDAGISel::SelectSMRDBaseOffset(SDValue Addr, SDValue &SBase,
20742096
SDValue *SOffset, SDValue *Offset,
2075-
bool Imm32Only,
2076-
bool IsBuffer) const {
2097+
bool Imm32Only, bool IsBuffer,
2098+
bool HasSOffset,
2099+
int64_t ImmOffset) const {
20772100
if (SOffset && Offset) {
20782101
assert(!Imm32Only && !IsBuffer);
20792102
SDValue B;
2080-
return SelectSMRDBaseOffset(Addr, B, nullptr, Offset) &&
2081-
SelectSMRDBaseOffset(B, SBase, SOffset, nullptr);
2103+
2104+
if (!SelectSMRDBaseOffset(Addr, B, nullptr, Offset, false, false, true))
2105+
return false;
2106+
2107+
int64_t ImmOff = 0;
2108+
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(*Offset))
2109+
ImmOff = C->getSExtValue();
2110+
2111+
return SelectSMRDBaseOffset(B, SBase, SOffset, nullptr, false, false, true,
2112+
ImmOff);
20822113
}
20832114

20842115
// A 32-bit (address + offset) should not cause unsigned 32-bit integer
@@ -2097,11 +2128,14 @@ bool AMDGPUDAGToDAGISel::SelectSMRDBaseOffset(SDValue Addr, SDValue &SBase,
20972128
}
20982129
if (!N0 || !N1)
20992130
return false;
2100-
if (SelectSMRDOffset(N1, SOffset, Offset, Imm32Only, IsBuffer)) {
2131+
2132+
if (SelectSMRDOffset(N1, SOffset, Offset, Imm32Only, IsBuffer, HasSOffset,
2133+
ImmOffset)) {
21012134
SBase = N0;
21022135
return true;
21032136
}
2104-
if (SelectSMRDOffset(N0, SOffset, Offset, Imm32Only, IsBuffer)) {
2137+
if (SelectSMRDOffset(N0, SOffset, Offset, Imm32Only, IsBuffer, HasSOffset,
2138+
ImmOffset)) {
21052139
SBase = N1;
21062140
return true;
21072141
}

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -150,6 +150,8 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {
150150
bool isFlatScratchBaseLegal(SDValue Addr) const;
151151
bool isFlatScratchBaseLegalSV(SDValue Addr) const;
152152
bool isFlatScratchBaseLegalSVImm(SDValue Addr) const;
153+
bool isSOffsetLegalWithImmOffset(SDValue *SOffset, bool Imm32Only,
154+
bool IsBuffer, int64_t ImmOffset = 0) const;
153155

154156
bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
155157
bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
@@ -192,11 +194,13 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {
192194

193195
bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue *SOffset,
194196
SDValue *Offset, bool Imm32Only = false,
195-
bool IsBuffer = false) const;
197+
bool IsBuffer = false, bool HasSOffset = false,
198+
int64_t ImmOffset = 0) const;
196199
SDValue Expand32BitAddress(SDValue Addr) const;
197200
bool SelectSMRDBaseOffset(SDValue Addr, SDValue &SBase, SDValue *SOffset,
198201
SDValue *Offset, bool Imm32Only = false,
199-
bool IsBuffer = false) const;
202+
bool IsBuffer = false, bool HasSOffset = false,
203+
int64_t ImmOffset = 0) const;
200204
bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue *SOffset,
201205
SDValue *Offset, bool Imm32Only = false) const;
202206
bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
@@ -208,6 +212,8 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {
208212
bool SelectSMRDBufferImm32(SDValue N, SDValue &Offset) const;
209213
bool SelectSMRDBufferSgprImm(SDValue N, SDValue &SOffset,
210214
SDValue &Offset) const;
215+
bool SelectSMRDPrefetchImm(SDValue Addr, SDValue &SBase,
216+
SDValue &Offset) const;
211217
bool SelectMOVRELOffset(SDValue Index, SDValue &Base, SDValue &Offset) const;
212218

213219
bool SelectVOP3ModsImpl(SDValue In, SDValue &Src, unsigned &SrcMods,

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Lines changed: 16 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4235,10 +4235,11 @@ bool AMDGPUInstructionSelector::selectSmrdOffset(MachineOperand &Root,
42354235
return false;
42364236

42374237
const GEPInfo &GEPI = AddrInfo[0];
4238-
std::optional<int64_t> EncodedImm =
4239-
AMDGPU::getSMRDEncodedOffset(STI, GEPI.Imm, false);
4238+
std::optional<int64_t> EncodedImm;
42404239

42414240
if (SOffset && Offset) {
4241+
EncodedImm = AMDGPU::getSMRDEncodedOffset(STI, GEPI.Imm, /*IsBuffer=*/false,
4242+
/*HasSOffset=*/true);
42424243
if (GEPI.SgprParts.size() == 1 && GEPI.Imm != 0 && EncodedImm &&
42434244
AddrInfo.size() > 1) {
42444245
const GEPInfo &GEPI2 = AddrInfo[1];
@@ -4248,13 +4249,26 @@ bool AMDGPUInstructionSelector::selectSmrdOffset(MachineOperand &Root,
42484249
Base = GEPI2.SgprParts[0];
42494250
*SOffset = OffsetReg;
42504251
*Offset = *EncodedImm;
4252+
if (*Offset >= 0 || !AMDGPU::hasSMRDSignedImmOffset(STI))
4253+
return true;
4254+
4255+
// For unbuffered smem loads, it is illegal for the Immediate Offset
4256+
// to be negative if the resulting (Offset + (M0 or SOffset or zero)
4257+
// is negative. Handle the case where the Immediate Offset + SOffset
4258+
// is negative.
4259+
auto SKnown = KB->getKnownBits(*SOffset);
4260+
if (*Offset + SKnown.getMinValue().getSExtValue() < 0)
4261+
return false;
4262+
42514263
return true;
42524264
}
42534265
}
42544266
}
42554267
return false;
42564268
}
42574269

4270+
EncodedImm = AMDGPU::getSMRDEncodedOffset(STI, GEPI.Imm, /*IsBuffer=*/false,
4271+
/*HasSOffset=*/false);
42584272
if (Offset && GEPI.SgprParts.size() == 1 && EncodedImm) {
42594273
Base = GEPI.SgprParts[0];
42604274
*Offset = *EncodedImm;

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Lines changed: 14 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,12 @@ namespace llvm {
156156

157157
namespace AMDGPU {
158158

159+
/// \returns true if the target supports signed immediate offset for SMRD
160+
/// instructions.
161+
bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST) {
162+
return isGFX9Plus(ST);
163+
}
164+
159165
/// \returns True if \p STI is AMDHSA.
160166
bool isHsaAbi(const MCSubtargetInfo &STI) {
161167
return STI.getTargetTriple().getOS() == Triple::AMDHSA;
@@ -2814,10 +2820,6 @@ static bool hasSMEMByteOffset(const MCSubtargetInfo &ST) {
28142820
return isGCN3Encoding(ST) || isGFX10Plus(ST);
28152821
}
28162822

2817-
static bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST) {
2818-
return isGFX9Plus(ST);
2819-
}
2820-
28212823
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
28222824
int64_t EncodedOffset) {
28232825
if (isGFX12Plus(ST))
@@ -2852,7 +2854,14 @@ uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST,
28522854
}
28532855

28542856
std::optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
2855-
int64_t ByteOffset, bool IsBuffer) {
2857+
int64_t ByteOffset, bool IsBuffer,
2858+
bool HasSOffset) {
2859+
// For unbuffered smem loads, it is illegal for the Immediate Offset to be
2860+
// negative if the resulting (Offset + (M0 or SOffset or zero) is negative.
2861+
// Handle case where SOffset is not present.
2862+
if (!IsBuffer && !HasSOffset && ByteOffset < 0 && hasSMRDSignedImmOffset(ST))
2863+
return std::nullopt;
2864+
28562865
if (isGFX12Plus(ST)) // 24 bit signed offsets
28572866
return isInt<24>(ByteOffset) ? std::optional<int64_t>(ByteOffset)
28582867
: std::nullopt;

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1247,6 +1247,7 @@ bool hasVOPD(const MCSubtargetInfo &STI);
12471247
bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI);
12481248
int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
12491249
unsigned hasKernargPreload(const MCSubtargetInfo &STI);
1250+
bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST);
12501251

12511252
/// Is Reg - scalar register
12521253
bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
@@ -1397,7 +1398,8 @@ uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
13971398
/// S_LOAD instructions have a signed offset, on other subtargets it is
13981399
/// unsigned. S_BUFFER has an unsigned offset for all subtargets.
13991400
std::optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
1400-
int64_t ByteOffset, bool IsBuffer);
1401+
int64_t ByteOffset, bool IsBuffer,
1402+
bool HasSOffset = false);
14011403

14021404
/// \return The encoding that can be used for a 32-bit literal offset in an SMRD
14031405
/// instruction. This is only useful on CI.s

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir

Lines changed: 18 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1234,7 +1234,15 @@ body: |
12341234
; GFX10: liveins: $sgpr0_sgpr1
12351235
; GFX10-NEXT: {{ $}}
12361236
; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
1237-
; GFX10-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], -1, 0 :: (load (s32), addrspace 4)
1237+
; GFX10-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -1
1238+
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
1239+
; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B]].sub0
1240+
; GFX10-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
1241+
; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B]].sub1
1242+
; GFX10-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[COPY2]], implicit-def $scc
1243+
; GFX10-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY3]], [[COPY4]], implicit-def dead $scc, implicit $scc
1244+
; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
1245+
; GFX10-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[REG_SEQUENCE]], 0, 0 :: (load (s32), addrspace 4)
12381246
; GFX10-NEXT: $sgpr0 = COPY [[S_LOAD_DWORD_IMM]]
12391247
%0:sgpr(p4) = COPY $sgpr0_sgpr1
12401248
%1:sgpr(s64) = G_CONSTANT i64 -1
@@ -1304,7 +1312,15 @@ body: |
13041312
; GFX10: liveins: $sgpr0_sgpr1
13051313
; GFX10-NEXT: {{ $}}
13061314
; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
1307-
; GFX10-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], -524288, 0 :: (load (s32), addrspace 4)
1315+
; GFX10-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -524288
1316+
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
1317+
; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B]].sub0
1318+
; GFX10-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
1319+
; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B]].sub1
1320+
; GFX10-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[COPY2]], implicit-def $scc
1321+
; GFX10-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY3]], [[COPY4]], implicit-def dead $scc, implicit $scc
1322+
; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
1323+
; GFX10-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[REG_SEQUENCE]], 0, 0 :: (load (s32), addrspace 4)
13081324
; GFX10-NEXT: $sgpr0 = COPY [[S_LOAD_DWORD_IMM]]
13091325
%0:sgpr(p4) = COPY $sgpr0_sgpr1
13101326
%1:sgpr(s64) = G_CONSTANT i64 -524288

‎llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -88,11 +88,13 @@ entry:
8888
ret void
8989
}
9090

91-
; GFX9_10 can use a signed immediate byte offset
91+
; GFX9+ can use a signed immediate byte offset but not without sgpr[offset]
9292
; GCN-LABEL: {{^}}smrd6:
9393
; SICIVI: s_add_u32 s{{[0-9]}}, s{{[0-9]}}, -4
9494
; SICIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x0
95-
; GFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], -0x4
95+
; GFX9_10: s_add_u32 s2, s2, -4
96+
; GFX9_10: s_addc_u32 s3, s3, -1
97+
; GFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x0
9698
define amdgpu_kernel void @smrd6(ptr addrspace(1) %out, ptr addrspace(4) %ptr) #0 {
9799
entry:
98100
%tmp = getelementptr i32, ptr addrspace(4) %ptr, i64 -1

‎llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-smem.ll

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -297,20 +297,26 @@ define amdgpu_cs void @test_sink_smem_offset_neg400(ptr addrspace(4) inreg %ptr,
297297
; GFX9: ; %bb.0: ; %entry
298298
; GFX9-NEXT: .LBB5_1: ; %loop
299299
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
300-
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
301-
; GFX9-NEXT: s_load_dword s3, s[0:1], -0x190
302300
; GFX9-NEXT: s_add_i32 s2, s2, -1
301+
; GFX9-NEXT: s_add_u32 s4, s0, 0xfffffe70
302+
; GFX9-NEXT: s_addc_u32 s5, s1, -1
303+
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
304+
; GFX9-NEXT: s_load_dword s3, s[4:5], 0x0
303305
; GFX9-NEXT: s_cmp_lg_u32 s2, 0
304306
; GFX9-NEXT: s_cbranch_scc1 .LBB5_1
305307
; GFX9-NEXT: ; %bb.2: ; %end
306308
; GFX9-NEXT: s_endpgm
307309
;
308310
; GFX12-LABEL: test_sink_smem_offset_neg400:
309311
; GFX12: ; %bb.0: ; %entry
312+
; GFX12-NEXT: s_movk_i32 s4, 0xfe70
313+
; GFX12-NEXT: s_mov_b32 s5, -1
314+
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
315+
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
310316
; GFX12-NEXT: .LBB5_1: ; %loop
311317
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
312318
; GFX12-NEXT: s_wait_kmcnt 0x0
313-
; GFX12-NEXT: s_load_b32 s3, s[0:1], -0x190
319+
; GFX12-NEXT: s_load_b32 s3, s[0:1], 0x0
314320
; GFX12-NEXT: s_add_co_i32 s2, s2, -1
315321
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
316322
; GFX12-NEXT: s_cmp_lg_u32 s2, 0

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