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AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (llvm#117380)
OPSEL ASM Syntax: opsel:[x,y,z] where, opsel[x] = Inst{11} = src0_modifier{2} opsel[y] = Inst{12} = src1_modifier{2} opsel[z] = Inst{14} = src0_modifier{3} Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax. Co-authored-by: Pravin Jagtap <[email protected]>
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‎llvm/lib/Target/AMDGPU/AMDGPU.td

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -384,11 +384,17 @@ def FeaturePermlane32Swap : SubtargetFeature<"permlane32-swap",
384384
"Has v_permlane32_swap_b32 instructions"
385385
>;
386386

387+
def FeatureFP8ConversionScaleInsts : SubtargetFeature<"fp8-cvt-scale-insts",
388+
"HasFP8ConversionScaleInsts",
389+
"true",
390+
"Has fp8 conversion scale instructions"
391+
>;
392+
387393
def FeatureGFX950Insts : SubtargetFeature<"gfx950-insts",
388394
"GFX950Insts",
389395
"true",
390396
"Additional instructions for GFX950+",
391-
[FeaturePermlane16Swap, FeaturePermlane32Swap]
397+
[FeaturePermlane16Swap, FeaturePermlane32Swap, FeatureFP8ConversionScaleInsts]
392398
>;
393399

394400
def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
@@ -1533,7 +1539,8 @@ def FeatureISAVersion9_5_Common : FeatureSet<
15331539
FeatureGFX950Insts,
15341540
FeaturePrngInst,
15351541
FeatureBF16ConversionInsts,
1536-
FeatureBitOp3Insts
1542+
FeatureBitOp3Insts,
1543+
FeatureFP8ConversionScaleInsts
15371544
])>;
15381545

15391546
def FeatureISAVersion9_4_0 : FeatureSet<
@@ -2410,6 +2417,9 @@ def HasBitOp3Insts : Predicate<"Subtarget->hasBitOp3Insts()">,
24102417
def HasPrngInst : Predicate<"Subtarget->hasPrngInst()">,
24112418
AssemblerPredicate<(all_of FeaturePrngInst)>;
24122419

2420+
def HasFP8ConversionScaleInsts : Predicate<"Subtarget->hasFP8ConversionScaleInsts()">,
2421+
AssemblerPredicate<(all_of FeatureFP8ConversionScaleInsts)>;
2422+
24132423
def HasGDS : Predicate<"Subtarget->hasGDS()">;
24142424

24152425
def HasGWS : Predicate<"Subtarget->hasGWS()">;

‎llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,7 @@ class AMDGPUSubtarget {
5050
bool GCN3Encoding = false;
5151
bool Has16BitInsts = false;
5252
bool HasTrue16BitInsts = false;
53+
bool HasFP8ConversionScaleInsts = false;
5354
bool EnableRealTrue16Insts = false;
5455
bool HasBF16ConversionInsts = false;
5556
bool HasMadMixInsts = false;
@@ -175,6 +176,8 @@ class AMDGPUSubtarget {
175176
return HasMadMixInsts;
176177
}
177178

179+
bool hasFP8ConversionScaleInsts() const { return HasFP8ConversionScaleInsts; }
180+
178181
bool hasMadMacF32Insts() const {
179182
return HasMadMacF32Insts || !isGCN();
180183
}

‎llvm/lib/Target/AMDGPU/VOP3Instructions.td

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -877,6 +877,24 @@ class VOP3_BITOP3_Profile<VOPProfile pfl, VOP3Features f> : VOP3_Profile<pfl, f>
877877
let AsmVOP3OpSel = !subst("$op_sel", "$bitop3$op_sel", getAsmVOP3OpSel<3, 0, 0, 0, 0, 0>.ret);
878878
}
879879

880+
class VOP3_CVT_SCALE_F1632_FP8BF8_Profile<ValueType DstTy> : VOP3_Profile<VOPProfile<[DstTy, i32, f32, untyped]>,
881+
VOP3_OPSEL> {
882+
let InsVOP3OpSel = (ins FP32InputMods:$src0_modifiers, Src0RC64:$src0,
883+
FP32InputMods:$src1_modifiers, Src1RC64:$src1,
884+
op_sel0:$op_sel);
885+
let HasClamp = 0;
886+
let HasSrc2 = 0;
887+
let HasSrc2Mods = 0;
888+
let HasExtVOP3DPP = 0;
889+
let HasOpSel = 1;
890+
let HasOMod = 0;
891+
}
892+
893+
let SubtargetPredicate = HasFP8ConversionScaleInsts, mayRaiseFPException = 0 in {
894+
defm V_CVT_SCALEF32_F16_FP8 : VOP3Inst<"v_cvt_scalef32_f16_fp8", VOP3_CVT_SCALE_F1632_FP8BF8_Profile<f16>>;
895+
defm V_CVT_SCALEF32_F32_FP8 : VOP3Inst<"v_cvt_scalef32_f32_fp8", VOP3_CVT_SCALE_F1632_FP8BF8_Profile<f32>>;
896+
}
897+
880898
let SubtargetPredicate = isGFX10Plus in {
881899
let isCommutable = 1, isReMaterializable = 1 in {
882900
defm V_XOR3_B32 : VOP3Inst <"v_xor3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
@@ -1776,3 +1794,7 @@ defm V_CVT_SR_BF8_F32 : VOP3OpSel_Real_gfx9_forced_opsel2 <0x2a5>;
17761794

17771795
defm V_BITOP3_B16 : VOP3_Real_BITOP3_gfx9<0x233, "v_bitop3_b16">;
17781796
defm V_BITOP3_B32 : VOP3_Real_BITOP3_gfx9<0x234, "v_bitop3_b32">;
1797+
let OtherPredicates = [HasFP8ConversionScaleInsts] in {
1798+
defm V_CVT_SCALEF32_F16_FP8 : VOP3OpSel_Real_gfx9 <0x24a>;
1799+
defm V_CVT_SCALEF32_F32_FP8 : VOP3OpSel_Real_gfx9 <0x23b>;
1800+
}

‎llvm/test/MC/AMDGPU/gfx950_asm_features.s

Lines changed: 192 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -117,3 +117,195 @@ v_permlane32_swap_b32_e64 v1, v2 bound_ctrl:1 fi:1
117117

118118
// FIXME: Swapped order not accepted
119119
// v_permlane32_swap_b32 v1, v2 fi:1 bound_ctrl:1
120+
121+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
122+
// GFX950: v_cvt_scalef32_f16_fp8 v1, v2, v3 ; encoding: [0x01,0x00,0x4a,0xd2,0x02,0x07,0x02,0x00]
123+
v_cvt_scalef32_f16_fp8 v1, v2, v3
124+
125+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
126+
// GFX950: v_cvt_scalef32_f16_fp8 v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x01,0x08,0x4a,0xd2,0x02,0x07,0x02,0x00]
127+
v_cvt_scalef32_f16_fp8 v1, v2, v3 op_sel:[1,0,0]
128+
129+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
130+
// GFX950: v_cvt_scalef32_f16_fp8 v1, v2, v3 op_sel:[0,1,0] ; encoding: [0x01,0x10,0x4a,0xd2,0x02,0x07,0x02,0x00]
131+
v_cvt_scalef32_f16_fp8 v1, v2, v3 op_sel:[0,1,0]
132+
133+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
134+
// GFX950: v_cvt_scalef32_f16_fp8 v1, v2, v3 op_sel:[1,1,0] ; encoding: [0x01,0x18,0x4a,0xd2,0x02,0x07,0x02,0x00]
135+
v_cvt_scalef32_f16_fp8 v1, v2, v3 op_sel:[1,1,0]
136+
137+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
138+
// GFX950: v_cvt_scalef32_f16_fp8 v1, v2, v3 op_sel:[0,0,1] ; encoding: [0x01,0x40,0x4a,0xd2,0x02,0x07,0x02,0x00]
139+
v_cvt_scalef32_f16_fp8 v1, v2, v3 op_sel:[0,0,1]
140+
141+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
142+
// GFX950: v_cvt_scalef32_f16_fp8 v1, v2, v3 op_sel:[1,0,1] ; encoding: [0x01,0x48,0x4a,0xd2,0x02,0x07,0x02,0x00]
143+
v_cvt_scalef32_f16_fp8 v1, v2, v3 op_sel:[1,0,1]
144+
145+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
146+
// GFX950: v_cvt_scalef32_f16_fp8 v1, v2, v3 op_sel:[0,1,1] ; encoding: [0x01,0x50,0x4a,0xd2,0x02,0x07,0x02,0x00]
147+
v_cvt_scalef32_f16_fp8 v1, v2, v3 op_sel:[0,1,1]
148+
149+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
150+
// GFX950: v_cvt_scalef32_f16_fp8 v1, v2, v3 op_sel:[1,1,1] ; encoding: [0x01,0x58,0x4a,0xd2,0x02,0x07,0x02,0x00]
151+
v_cvt_scalef32_f16_fp8 v1, v2, v3 op_sel:[1,1,1]
152+
153+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
154+
// GFX950: v_cvt_scalef32_f16_fp8 v1, s1, v3 ; encoding: [0x01,0x00,0x4a,0xd2,0x01,0x06,0x02,0x00]
155+
v_cvt_scalef32_f16_fp8 v1, s1, v3
156+
157+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
158+
// GFX950: v_cvt_scalef32_f16_fp8 v1, s2, v3 op_sel:[1,0,0] ; encoding: [0x01,0x08,0x4a,0xd2,0x02,0x06,0x02,0x00]
159+
v_cvt_scalef32_f16_fp8 v1, s2, v3 op_sel:[1,0,0]
160+
161+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
162+
// GFX950: v_cvt_scalef32_f16_fp8 v1, s3, v3 op_sel:[0,1,0] ; encoding: [0x01,0x10,0x4a,0xd2,0x03,0x06,0x02,0x00]
163+
v_cvt_scalef32_f16_fp8 v1, s3, v3 op_sel:[0,1,0]
164+
165+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
166+
// GFX950: v_cvt_scalef32_f16_fp8 v1, s4, v3 op_sel:[1,1,0] ; encoding: [0x01,0x18,0x4a,0xd2,0x04,0x06,0x02,0x00]
167+
v_cvt_scalef32_f16_fp8 v1, s4, v3 op_sel:[1,1,0]
168+
169+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
170+
// GFX950: v_cvt_scalef32_f16_fp8 v1, s1, v3 op_sel:[0,0,1] ; encoding: [0x01,0x40,0x4a,0xd2,0x01,0x06,0x02,0x00]
171+
v_cvt_scalef32_f16_fp8 v1, s1, v3 op_sel:[0,0,1]
172+
173+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
174+
// GFX950: v_cvt_scalef32_f16_fp8 v1, s2, v3 op_sel:[1,0,1] ; encoding: [0x01,0x48,0x4a,0xd2,0x02,0x06,0x02,0x00]
175+
v_cvt_scalef32_f16_fp8 v1, s2, v3 op_sel:[1,0,1]
176+
177+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
178+
// GFX950: v_cvt_scalef32_f16_fp8 v1, s3, v3 op_sel:[0,1,1] ; encoding: [0x01,0x50,0x4a,0xd2,0x03,0x06,0x02,0x00]
179+
v_cvt_scalef32_f16_fp8 v1, s3, v3 op_sel:[0,1,1]
180+
181+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
182+
// GFX950: v_cvt_scalef32_f16_fp8 v1, s4, v3 op_sel:[1,1,1] ; encoding: [0x01,0x58,0x4a,0xd2,0x04,0x06,0x02,0x00]
183+
v_cvt_scalef32_f16_fp8 v1, s4, v3 op_sel:[1,1,1]
184+
185+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
186+
// GFX950: v_cvt_scalef32_f16_fp8 v1, 11, v3 ; encoding: [0x01,0x00,0x4a,0xd2,0x8b,0x06,0x02,0x00]
187+
v_cvt_scalef32_f16_fp8 v1, 11, v3
188+
189+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
190+
// GFX950: v_cvt_scalef32_f16_fp8 v1, 22, v3 op_sel:[1,0,0] ; encoding: [0x01,0x08,0x4a,0xd2,0x96,0x06,0x02,0x00]
191+
v_cvt_scalef32_f16_fp8 v1, 22, v3 op_sel:[1,0,0]
192+
193+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
194+
// GFX950: v_cvt_scalef32_f16_fp8 v1, 33, v3 op_sel:[0,1,0] ; encoding: [0x01,0x10,0x4a,0xd2,0xa1,0x06,0x02,0x00]
195+
v_cvt_scalef32_f16_fp8 v1, 33, v3 op_sel:[0,1,0]
196+
197+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
198+
// GFX950: v_cvt_scalef32_f16_fp8 v1, 44, v3 op_sel:[1,1,0] ; encoding: [0x01,0x18,0x4a,0xd2,0xac,0x06,0x02,0x00]
199+
v_cvt_scalef32_f16_fp8 v1, 44, v3 op_sel:[1,1,0]
200+
201+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
202+
// GFX950: v_cvt_scalef32_f16_fp8 v1, 11, v3 op_sel:[0,1,1] ; encoding: [0x01,0x50,0x4a,0xd2,0x8b,0x06,0x02,0x00]
203+
v_cvt_scalef32_f16_fp8 v1, 11, v3 op_sel:[0,1,1]
204+
205+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
206+
// GFX950: v_cvt_scalef32_f16_fp8 v1, 22, v3 op_sel:[1,0,1] ; encoding: [0x01,0x48,0x4a,0xd2,0x96,0x06,0x02,0x00]
207+
v_cvt_scalef32_f16_fp8 v1, 22, v3 op_sel:[1,0,1]
208+
209+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
210+
// GFX950: v_cvt_scalef32_f16_fp8 v1, 33, v3 op_sel:[0,1,1] ; encoding: [0x01,0x50,0x4a,0xd2,0xa1,0x06,0x02,0x00]
211+
v_cvt_scalef32_f16_fp8 v1, 33, v3 op_sel:[0,1,1]
212+
213+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
214+
// GFX950: v_cvt_scalef32_f16_fp8 v1, 44, v3 op_sel:[1,1,1] ; encoding: [0x01,0x58,0x4a,0xd2,0xac,0x06,0x02,0x00]
215+
v_cvt_scalef32_f16_fp8 v1, 44, v3 op_sel:[1,1,1]
216+
217+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
218+
// GFX950: v_cvt_scalef32_f32_fp8 v1, v2, v3 ; encoding: [0x01,0x00,0x3b,0xd2,0x02,0x07,0x02,0x00]
219+
v_cvt_scalef32_f32_fp8 v1, v2, v3
220+
221+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
222+
// GFX950: v_cvt_scalef32_f32_fp8 v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x01,0x08,0x3b,0xd2,0x02,0x07,0x02,0x00]
223+
v_cvt_scalef32_f32_fp8 v1, v2, v3 op_sel:[1,0,0]
224+
225+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
226+
// GFX950: v_cvt_scalef32_f32_fp8 v1, v2, v3 op_sel:[0,1,0] ; encoding: [0x01,0x10,0x3b,0xd2,0x02,0x07,0x02,0x00]
227+
v_cvt_scalef32_f32_fp8 v1, v2, v3 op_sel:[0,1,0]
228+
229+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
230+
// GFX950: v_cvt_scalef32_f32_fp8 v1, v2, v3 op_sel:[1,1,0] ; encoding: [0x01,0x18,0x3b,0xd2,0x02,0x07,0x02,0x00]
231+
v_cvt_scalef32_f32_fp8 v1, v2, v3 op_sel:[1,1,0]
232+
233+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
234+
// GFX950: v_cvt_scalef32_f32_fp8 v1, v2, v3 op_sel:[0,0,1] ; encoding: [0x01,0x40,0x3b,0xd2,0x02,0x07,0x02,0x00]
235+
v_cvt_scalef32_f32_fp8 v1, v2, v3 op_sel:[0,0,1]
236+
237+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
238+
// GFX950: v_cvt_scalef32_f32_fp8 v1, v2, v3 op_sel:[1,0,1] ; encoding: [0x01,0x48,0x3b,0xd2,0x02,0x07,0x02,0x00]
239+
v_cvt_scalef32_f32_fp8 v1, v2, v3 op_sel:[1,0,1]
240+
241+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
242+
// GFX950: v_cvt_scalef32_f32_fp8 v1, v2, v3 op_sel:[0,1,1] ; encoding: [0x01,0x50,0x3b,0xd2,0x02,0x07,0x02,0x00]
243+
v_cvt_scalef32_f32_fp8 v1, v2, v3 op_sel:[0,1,1]
244+
245+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
246+
// GFX950: v_cvt_scalef32_f32_fp8 v1, v2, v3 op_sel:[1,1,1] ; encoding: [0x01,0x58,0x3b,0xd2,0x02,0x07,0x02,0x00]
247+
v_cvt_scalef32_f32_fp8 v1, v2, v3 op_sel:[1,1,1]
248+
249+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
250+
// GFX950: v_cvt_scalef32_f32_fp8 v1, s1, v3 ; encoding: [0x01,0x00,0x3b,0xd2,0x01,0x06,0x02,0x00]
251+
v_cvt_scalef32_f32_fp8 v1, s1, v3
252+
253+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
254+
// GFX950: v_cvt_scalef32_f32_fp8 v1, s2, v3 op_sel:[1,0,0] ; encoding: [0x01,0x08,0x3b,0xd2,0x02,0x06,0x02,0x00]
255+
v_cvt_scalef32_f32_fp8 v1, s2, v3 op_sel:[1,0,0]
256+
257+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
258+
// GFX950: v_cvt_scalef32_f32_fp8 v1, s3, v3 op_sel:[0,1,0] ; encoding: [0x01,0x10,0x3b,0xd2,0x03,0x06,0x02,0x00]
259+
v_cvt_scalef32_f32_fp8 v1, s3, v3 op_sel:[0,1,0]
260+
261+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
262+
// GFX950: v_cvt_scalef32_f32_fp8 v1, s4, v3 op_sel:[1,1,0] ; encoding: [0x01,0x18,0x3b,0xd2,0x04,0x06,0x02,0x00]
263+
v_cvt_scalef32_f32_fp8 v1, s4, v3 op_sel:[1,1,0]
264+
265+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
266+
// GFX950: v_cvt_scalef32_f32_fp8 v1, s1, v3 op_sel:[0,0,1] ; encoding: [0x01,0x40,0x3b,0xd2,0x01,0x06,0x02,0x00]
267+
v_cvt_scalef32_f32_fp8 v1, s1, v3 op_sel:[0,0,1]
268+
269+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
270+
// GFX950: v_cvt_scalef32_f32_fp8 v1, s2, v3 op_sel:[1,0,1] ; encoding: [0x01,0x48,0x3b,0xd2,0x02,0x06,0x02,0x00]
271+
v_cvt_scalef32_f32_fp8 v1, s2, v3 op_sel:[1,0,1]
272+
273+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
274+
// GFX950: v_cvt_scalef32_f32_fp8 v1, s3, v3 op_sel:[0,1,1] ; encoding: [0x01,0x50,0x3b,0xd2,0x03,0x06,0x02,0x00]
275+
v_cvt_scalef32_f32_fp8 v1, s3, v3 op_sel:[0,1,1]
276+
277+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
278+
// GFX950: v_cvt_scalef32_f32_fp8 v1, s4, v3 op_sel:[1,1,1] ; encoding: [0x01,0x58,0x3b,0xd2,0x04,0x06,0x02,0x00]
279+
v_cvt_scalef32_f32_fp8 v1, s4, v3 op_sel:[1,1,1]
280+
281+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
282+
// GFX950: v_cvt_scalef32_f32_fp8 v1, 11, v3 ; encoding: [0x01,0x00,0x3b,0xd2,0x8b,0x06,0x02,0x00]
283+
v_cvt_scalef32_f32_fp8 v1, 11, v3
284+
285+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
286+
// GFX950: v_cvt_scalef32_f32_fp8 v1, 22, v3 op_sel:[1,0,0] ; encoding: [0x01,0x08,0x3b,0xd2,0x96,0x06,0x02,0x00]
287+
v_cvt_scalef32_f32_fp8 v1, 22, v3 op_sel:[1,0,0]
288+
289+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
290+
// GFX950: v_cvt_scalef32_f32_fp8 v1, 33, v3 op_sel:[0,1,0] ; encoding: [0x01,0x10,0x3b,0xd2,0xa1,0x06,0x02,0x00]
291+
v_cvt_scalef32_f32_fp8 v1, 33, v3 op_sel:[0,1,0]
292+
293+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
294+
// GFX950: v_cvt_scalef32_f32_fp8 v1, 44, v3 op_sel:[1,1,0] ; encoding: [0x01,0x18,0x3b,0xd2,0xac,0x06,0x02,0x00]
295+
v_cvt_scalef32_f32_fp8 v1, 44, v3 op_sel:[1,1,0]
296+
297+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
298+
// GFX950: v_cvt_scalef32_f32_fp8 v1, 11, v3 op_sel:[0,0,1] ; encoding: [0x01,0x40,0x3b,0xd2,0x8b,0x06,0x02,0x00]
299+
v_cvt_scalef32_f32_fp8 v1, 11, v3 op_sel:[0,0,1]
300+
301+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
302+
// GFX950: v_cvt_scalef32_f32_fp8 v1, 22, v3 op_sel:[1,0,1] ; encoding: [0x01,0x48,0x3b,0xd2,0x96,0x06,0x02,0x00]
303+
v_cvt_scalef32_f32_fp8 v1, 22, v3 op_sel:[1,0,1]
304+
305+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
306+
// GFX950: v_cvt_scalef32_f32_fp8 v1, 33, v3 op_sel:[0,1,1] ; encoding: [0x01,0x50,0x3b,0xd2,0xa1,0x06,0x02,0x00]
307+
v_cvt_scalef32_f32_fp8 v1, 33, v3 op_sel:[0,1,1]
308+
309+
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
310+
// GFX950: v_cvt_scalef32_f32_fp8 v1, 44, v3 op_sel:[1,1,1] ; encoding: [0x01,0x58,0x3b,0xd2,0xac,0x06,0x02,0x00]
311+
v_cvt_scalef32_f32_fp8 v1, 44, v3 op_sel:[1,1,1]

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