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[IndVars] Add tests showing missed simplifications.
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‎llvm/test/Transforms/IndVarSimplify/simplify-icmp-operands-order.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -p indvars -S %s | FileCheck %s
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target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
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declare void @use(ptr)
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declare void @use.i64(i64)
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define i64 @test_simplifycompare_rhs_constant(i64 %num_bytes, ptr %src) {
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; CHECK-LABEL: define i64 @test_simplifycompare_rhs_constant(
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; CHECK-SAME: i64 [[NUM_BYTES:%.*]], ptr [[SRC:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp ne i64 [[NUM_BYTES]], 0
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; CHECK-NEXT: [[COND_I:%.*]] = zext i1 [[CMP_NOT_I]] to i64
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 1, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
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; CHECK-NEXT: [[C_0:%.*]] = icmp ule i64 [[IV]], [[COND_I]]
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[C_0]])
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; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr i32, ptr [[SRC]], i64 [[IV]]
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; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP_SRC]], align 4
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; CHECK-NEXT: [[C_1:%.*]] = icmp eq i32 [[L]], 0
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; CHECK-NEXT: br i1 [[C_1]], label %[[THEN:.*]], label %[[LOOP_LATCH]]
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; CHECK: [[THEN]]:
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; CHECK-NEXT: call void @use(ptr [[SRC]])
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; CHECK-NEXT: br label %[[LOOP_LATCH]]
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; CHECK: [[LOOP_LATCH]]:
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: br label %[[LOOP]]
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;
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entry:
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%cmp.not.i = icmp ne i64 %num_bytes, 0
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%cond.i = zext i1 %cmp.not.i to i64
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br label %loop
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loop:
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%iv = phi i64 [ 1, %entry ], [ %iv.next, %loop.latch ]
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%c.0 = icmp ule i64 %iv, %cond.i
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tail call void @llvm.assume(i1 %c.0)
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%gep.src = getelementptr i32, ptr %src, i64 %iv
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%l = load i32, ptr %gep.src, align 4
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%c.1 = icmp eq i32 %l, 0
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br i1 %c.1, label %then, label %loop.latch
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then:
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call void @use(ptr %src)
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br label %loop.latch
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loop.latch:
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%iv.next = add i64 %iv, 1
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br label %loop
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}
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define void @test_simplifycompare_rhs_not_constant1() {
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; CHECK-LABEL: define void @test_simplifycompare_rhs_not_constant1() {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[P:%.*]] = alloca i64, align 8
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[P]], %[[ENTRY]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 -8
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; CHECK-NEXT: call void @use(ptr [[PTR_IV]])
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; CHECK-NEXT: [[EC:%.*]] = icmp ult ptr [[PTR_IV_NEXT]], [[P]]
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; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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%p = alloca i64, align 8
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br label %loop
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loop:
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%ptr.iv = phi ptr [ %p, %entry ], [ %ptr.iv.next, %loop ]
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%ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 -8
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call void @use(ptr %ptr.iv)
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%ec = icmp ult ptr %ptr.iv.next, %p
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br i1 %ec, label %exit, label %loop
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exit:
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ret void
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}
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define void @test_simplifycompare_rhs_not_constant2(i32 %x) {
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; CHECK-LABEL: define void @test_simplifycompare_rhs_not_constant2(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]
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; CHECK: [[OUTER_HEADER_LOOPEXIT:.*]]:
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; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw i64 [[INDVARS_IV:%.*]], 2
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; CHECK-NEXT: br label %[[OUTER_HEADER]]
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; CHECK: [[OUTER_HEADER]]:
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; CHECK-NEXT: [[INDVARS_IV]] = phi i64 [ [[INDVARS_IV_NEXT]], %[[OUTER_HEADER_LOOPEXIT]] ], [ 0, %[[ENTRY]] ]
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; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_1_NEXT:%.*]], %[[OUTER_HEADER_LOOPEXIT]] ]
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; CHECK-NEXT: [[C_1:%.*]] = icmp sgt i32 [[X]], 0
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; CHECK-NEXT: br i1 [[C_1]], label %[[EXIT_LOOP_PREHEADER:.*]], label %[[OUTER_LATCH_PREHEADER:.*]]
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; CHECK: [[EXIT_LOOP_PREHEADER]]:
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; CHECK-NEXT: [[INDVARS_IV_LCSSA:%.*]] = phi i64 [ [[INDVARS_IV]], %[[OUTER_HEADER]] ]
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; CHECK-NEXT: br label %[[EXIT_LOOP:.*]]
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; CHECK: [[OUTER_LATCH_PREHEADER]]:
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; CHECK-NEXT: [[IV_1_NEXT]] = add nuw nsw i32 [[IV_1]], 2
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; CHECK-NEXT: br label %[[OUTER_LATCH:.*]]
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; CHECK: [[OUTER_LATCH]]:
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; CHECK-NEXT: [[P:%.*]] = phi i32 [ 0, %[[OUTER_LATCH_PREHEADER]] ], [ [[X]], %[[OUTER_LATCH]] ]
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; CHECK-NEXT: [[C_2:%.*]] = icmp ult i32 [[P]], [[IV_1_NEXT]]
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; CHECK-NEXT: br i1 [[C_2]], label %[[OUTER_LATCH]], label %[[OUTER_HEADER_LOOPEXIT]]
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; CHECK: [[EXIT_LOOP]]:
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; CHECK-NEXT: [[INDVARS_IV1:%.*]] = phi i64 [ [[INDVARS_IV_LCSSA]], %[[EXIT_LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT2:%.*]], %[[EXIT_LOOP]] ]
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; CHECK-NEXT: call void @use.i64(i64 [[INDVARS_IV1]])
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; CHECK-NEXT: [[INDVARS_IV_NEXT2]] = add nuw nsw i64 [[INDVARS_IV1]], 1
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; CHECK-NEXT: br label %[[EXIT_LOOP]]
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;
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entry:
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br label %outer.header
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outer.header:
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%iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %outer.latch ]
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%c.1 = icmp sgt i32 %x, 0
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br i1 %c.1, label %exit.loop, label %outer.latch.preheader
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outer.latch.preheader:
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%iv.1.next = add nsw i32 %iv.1, 2
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br label %outer.latch
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outer.latch:
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%p = phi i32 [ 0, %outer.latch.preheader ], [ %x, %outer.latch ]
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%c.2 = icmp ult i32 %p, %iv.1.next
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br i1 %c.2, label %outer.latch, label %outer.header
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exit.loop:
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%iv.2 = phi i32 [ %iv.1, %outer.header ], [ %iv.2.next, %exit.loop ]
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%iv.2.ext = zext i32 %iv.2 to i64
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call void @use.i64(i64 %iv.2.ext)
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%iv.2.next = add nsw i32 %iv.2, 1
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br label %exit.loop
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}
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define void @test_simplifycompare_rhs_addrec(i32 %x) {
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; CHECK-LABEL: define void @test_simplifycompare_rhs_addrec(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]
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; CHECK: [[OUTER_HEADER_LOOPEXIT:.*]]:
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; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV:%.*]], 2
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; CHECK-NEXT: br label %[[OUTER_HEADER]]
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; CHECK: [[OUTER_HEADER]]:
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; CHECK-NEXT: [[INDVARS_IV]] = phi i64 [ [[INDVARS_IV_NEXT]], %[[OUTER_HEADER_LOOPEXIT]] ], [ 0, %[[ENTRY]] ]
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; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ 2, %[[ENTRY]] ], [ [[IV_1_NEXT:%.*]], %[[OUTER_HEADER_LOOPEXIT]] ]
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; CHECK-NEXT: [[C_1:%.*]] = icmp sgt i32 [[X]], 0
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; CHECK-NEXT: br i1 [[C_1]], label %[[OUTER_EXIT:.*]], label %[[OUTER_LATCH_PREHEADER:.*]]
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; CHECK: [[OUTER_LATCH_PREHEADER]]:
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; CHECK-NEXT: [[IV_1_NEXT]] = add nuw nsw i32 [[IV_1]], 2
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; CHECK-NEXT: br label %[[OUTER_LATCH:.*]]
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; CHECK: [[OUTER_LATCH]]:
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; CHECK-NEXT: [[P:%.*]] = phi i32 [ [[X]], %[[OUTER_LATCH]] ], [ 0, %[[OUTER_LATCH_PREHEADER]] ]
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; CHECK-NEXT: [[C_2:%.*]] = icmp ult i32 [[P]], [[IV_1_NEXT]]
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; CHECK-NEXT: br i1 [[C_2]], label %[[OUTER_LATCH]], label %[[OUTER_HEADER_LOOPEXIT]]
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; CHECK: [[OUTER_EXIT]]:
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; CHECK-NEXT: [[INDVARS_IV_LCSSA:%.*]] = phi i64 [ [[INDVARS_IV]], %[[OUTER_HEADER]] ]
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; CHECK-NEXT: br label %[[EXIT_LOOP:.*]]
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; CHECK: [[EXIT_LOOP]]:
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; CHECK-NEXT: [[INDVARS_IV1:%.*]] = phi i64 [ [[INDVARS_IV_NEXT2:%.*]], %[[EXIT_LOOP]] ], [ [[INDVARS_IV_LCSSA]], %[[OUTER_EXIT]] ]
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; CHECK-NEXT: call void @use.i64(i64 [[INDVARS_IV1]])
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; CHECK-NEXT: [[INDVARS_IV_NEXT2]] = add nuw nsw i64 [[INDVARS_IV1]], 1
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; CHECK-NEXT: br label %[[EXIT_LOOP]]
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;
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entry:
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br label %outer.header
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outer.header:
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%iv.1 = phi i32 [ 2, %entry ], [ %iv.1.next, %outer.latch ]
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%c.1 = icmp sgt i32 %x, 0
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br i1 %c.1, label %outer.exit, label %outer.latch.preheader
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outer.latch.preheader:
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%iv.1.next = add nuw nsw i32 %iv.1, 2
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br label %outer.latch
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outer.latch:
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%p = phi i32 [ %x, %outer.latch ], [ 0, %outer.latch.preheader ]
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%c.2 = icmp ult i32 %p, %iv.1.next
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br i1 %c.2, label %outer.latch, label %outer.header
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outer.exit:
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%sub = add nsw i32 %iv.1, -2
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br label %exit.loop
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exit.loop:
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%iv.2 = phi i32 [ %sub, %outer.exit ], [ %iv.2.next, %exit.loop ]
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%iv.2.ext = sext i32 %iv.2 to i64
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call void @use.i64(i64 %iv.2.ext)
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%iv.2.next = add nsw i32 %iv.2, 1
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br label %exit.loop
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}

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