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merge main into amd-staging (llvm#1859)
2 parents b90f641 + 45a347a commit d27bc17

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‎.github/workflows/pr-code-format.yml

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -73,10 +73,6 @@ jobs:
7373
START_REV: ${{ github.event.pull_request.base.sha }}
7474
END_REV: ${{ github.event.pull_request.head.sha }}
7575
CHANGED_FILES: ${{ steps.changed-files.outputs.all_changed_files }}
76-
# TODO(boomanaiden154): Once clang v18 is released, we should be able
77-
# to take advantage of the new --diff_from_common_commit option
78-
# explicitly in code-format-helper.py and not have to diff starting at
79-
# the merge base.
8076
# Create an empty comments file so the pr-write job doesn't fail.
8177
run: |
8278
echo "[]" > comments &&

‎.github/workflows/premerge.yaml

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,6 @@ jobs:
6565
export CXX=/opt/llvm/bin/clang++
6666
6767
./.ci/monolithic-linux.sh "${projects_to_build}" "${project_check_targets}" "${runtimes_to_build}" "${runtimes_check_targets}"
68-
- name: "Upload artifact"
6968
- name: Upload Artifacts
7069
uses: actions/upload-artifact@65c4c4a1ddee5b72f698fdd19549f0f0fb45cf08 # v4.6.0
7170
with:

‎clang/docs/ReleaseNotes.rst

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -666,6 +666,8 @@ RISC-V Support
666666
Qualcomm's `Xqciint` extension to save and restore some GPRs in interrupt
667667
service routines.
668668

669+
- `Zicsr` / `Zifencei` are allowed to be duplicated in the presence of `g` in `-march`.
670+
669671
CUDA/HIP Language Changes
670672
^^^^^^^^^^^^^^^^^^^^^^^^^
671673

‎clang/lib/AST/ByteCode/InterpBuiltin.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1641,6 +1641,13 @@ static bool interp__builtin_operator_delete(InterpState &S, CodePtr OpPC,
16411641

16421642
Source = Ptr.getDeclDesc()->asExpr();
16431643
BlockToDelete = Ptr.block();
1644+
1645+
if (!BlockToDelete->isDynamic()) {
1646+
S.FFDiag(Call, diag::note_constexpr_delete_not_heap_alloc)
1647+
<< Ptr.toDiagnosticString(S.getASTContext());
1648+
if (const auto *D = Ptr.getFieldDesc()->asDecl())
1649+
S.Note(D->getLocation(), diag::note_declared_at);
1650+
}
16441651
}
16451652
assert(BlockToDelete);
16461653

‎clang/lib/Headers/avx512fp16intrin.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -559,7 +559,8 @@ static __inline__ __m512h __DEFAULT_FN_ATTRS512 _mm512_abs_ph(__m512h __A) {
559559
}
560560

561561
static __inline__ __m512h __DEFAULT_FN_ATTRS512 _mm512_conj_pch(__m512h __A) {
562-
return (__m512h)_mm512_xor_ps((__m512)__A, _mm512_set1_ps(-0.0f));
562+
return (__m512h)_mm512_xor_epi32((__m512i)__A,
563+
_mm512_set1_epi32(-2147483648));
563564
}
564565

565566
static __inline__ __m512h __DEFAULT_FN_ATTRS512

‎clang/test/AST/ByteCode/new-delete.cpp

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -610,7 +610,8 @@ namespace std {
610610
}
611611
constexpr void deallocate(void *p) {
612612
__builtin_operator_delete(p); // both-note 2{{std::allocator<...>::deallocate' used to delete pointer to object allocated with 'new'}} \
613-
// both-note {{used to delete a null pointer}}
613+
// both-note {{used to delete a null pointer}} \
614+
// both-note {{delete of pointer '&no_deallocate_nonalloc' that does not point to a heap-allocated object}}
614615
}
615616
};
616617
template<typename T, typename ...Args>
@@ -1004,6 +1005,10 @@ namespace WrongFrame {
10041005

10051006
}
10061007

1008+
constexpr int no_deallocate_nonalloc = (std::allocator<int>().deallocate((int*)&no_deallocate_nonalloc), 1); // both-error {{constant expression}} \
1009+
// both-note {{in call}} \
1010+
// both-note {{declared here}}
1011+
10071012
#else
10081013
/// Make sure we reject this prior to C++20
10091014
constexpr int a() { // both-error {{never produces a constant expression}}

‎clang/test/CodeGen/X86/avx512fp16-builtins-constrained-cmp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512fp16 -emit-llvm -ffp-exception-behavior=strict -o - -Wall -Werror | FileCheck %s
1+
// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512fp16 -target-feature +avx512vl -emit-llvm -ffp-exception-behavior=strict -o - -Wall -Werror | FileCheck %s
22

33
#include <immintrin.h>
44

‎clang/test/CodeGen/X86/avx512fp16-builtins.c

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -689,24 +689,24 @@ __m512h test_mm512_abs_ph(__m512h a) {
689689

690690
__m512h test_mm512_conj_pch(__m512h __A) {
691691
// CHECK-LABEL: @test_mm512_conj_pch
692-
// CHECK: %{{.*}} = bitcast <32 x half> %{{.*}} to <16 x float>
693-
// CHECK: %{{.*}} = bitcast <16 x float> %{{.*}} to <16 x i32>
694-
// CHECK: %{{.*}} = bitcast <16 x float> %{{.*}} to <16 x i32>
692+
// CHECK: %{{.*}} = bitcast <32 x half> %{{.*}} to <8 x i64>
693+
// CHECK: %{{.*}} = bitcast <8 x i64> %{{.*}} to <16 x i32>
694+
// CHECK: %{{.*}} = bitcast <8 x i64> %{{.*}} to <16 x i32>
695695
// CHECK: %{{.*}} = xor <16 x i32> %{{.*}}, %{{.*}}
696-
// CHECK: %{{.*}} = bitcast <16 x i32> %{{.*}} to <16 x float>
697-
// CHECK: %{{.*}} = bitcast <16 x float> %{{.*}} to <32 x half>
696+
// CHECK: %{{.*}} = bitcast <16 x i32> %{{.*}} to <8 x i64>
697+
// CHECK: %{{.*}} = bitcast <8 x i64> %{{.*}} to <32 x half>
698698
return _mm512_conj_pch(__A);
699699
}
700700

701701
__m512h test_mm512_mask_conj_pch(__m512h __W, __mmask32 __U, __m512h __A) {
702702
// CHECK-LABEL: @test_mm512_mask_conj_pch
703703
// CHECK: %{{.*}} = trunc i32 %{{.*}} to i16
704-
// CHECK: %{{.*}} = bitcast <32 x half> %{{.*}} to <16 x float>
705-
// CHECK: %{{.*}} = bitcast <16 x float> %{{.*}} to <16 x i32>
706-
// CHECK: %{{.*}} = bitcast <16 x float> %{{.*}} to <16 x i32>
704+
// CHECK: %{{.*}} = bitcast <32 x half> %{{.*}} to <8 x i64>
705+
// CHECK: %{{.*}} = bitcast <8 x i64> %{{.*}} to <16 x i32>
706+
// CHECK: %{{.*}} = bitcast <8 x i64> %{{.*}} to <16 x i32>
707707
// CHECK: %{{.*}} = xor <16 x i32> %{{.*}}, %{{.*}}
708-
// CHECK: %{{.*}} = bitcast <16 x i32> %{{.*}} to <16 x float>
709-
// CHECK: %{{.*}} = bitcast <16 x float> %{{.*}} to <32 x half>
708+
// CHECK: %{{.*}} = bitcast <16 x i32> %{{.*}} to <8 x i64>
709+
// CHECK: %{{.*}} = bitcast <8 x i64> %{{.*}} to <32 x half>
710710
// CHECK: %{{.*}} = bitcast <32 x half> %{{.*}} to <16 x float>
711711
// CHECK: %{{.*}} = bitcast i16 %{{.*}} to <16 x i1>
712712
// CHECK: %{{.*}} = select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
@@ -717,12 +717,12 @@ __m512h test_mm512_mask_conj_pch(__m512h __W, __mmask32 __U, __m512h __A) {
717717
__m512h test_mm512_maskz_conj_pch(__mmask32 __U, __m512h __A) {
718718
// CHECK-LABEL: @test_mm512_maskz_conj_pch
719719
// CHECK: %{{.*}} = trunc i32 %{{.*}} to i16
720-
// CHECK: %{{.*}} = bitcast <32 x half> %{{.*}} to <16 x float>
721-
// CHECK: %{{.*}} = bitcast <16 x float> %{{.*}} to <16 x i32>
722-
// CHECK: %{{.*}} = bitcast <16 x float> %{{.*}} to <16 x i32>
720+
// CHECK: %{{.*}} = bitcast <32 x half> %{{.*}} to <8 x i64>
721+
// CHECK: %{{.*}} = bitcast <8 x i64> %{{.*}} to <16 x i32>
722+
// CHECK: %{{.*}} = bitcast <8 x i64> %{{.*}} to <16 x i32>
723723
// CHECK: %{{.*}} = xor <16 x i32> %{{.*}}, %{{.*}}
724-
// CHECK: %{{.*}} = bitcast <16 x i32> %{{.*}} to <16 x float>
725-
// CHECK: %{{.*}} = bitcast <16 x float> %{{.*}} to <32 x half>
724+
// CHECK: %{{.*}} = bitcast <16 x i32> %{{.*}} to <8 x i64>
725+
// CHECK: %{{.*}} = bitcast <8 x i64> %{{.*}} to <32 x half>
726726
// CHECK: %{{.*}} = bitcast i16 %{{.*}} to <16 x i1>
727727
// CHECK: %{{.*}} = select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
728728
// CHECK: %{{.*}} = bitcast <16 x float> %{{.*}} to <32 x half>

‎clang/test/Preprocessor/x86_target_features.c

Lines changed: 2 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -596,31 +596,24 @@
596596
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512fp16 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512FP16 %s
597597

598598
// AVX512FP16: #define __AVX512BW__ 1
599-
// AVX512FP16: #define __AVX512DQ__ 1
600599
// AVX512FP16: #define __AVX512FP16__ 1
601-
// AVX512FP16: #define __AVX512VL__ 1
602-
// AVX512FP16: #define __EVEX256__ 1
603600
// AVX512FP16: #define __EVEX512__ 1
604601

605602
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512fp16 -mno-avx512vl -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512FP16NOAVX512VL %s
606603

607-
// AVX512FP16NOAVX512VL-NOT: #define __AVX512FP16__ 1
608-
// AVX512FP16NOAVX512VL-NOT: #define __AVX512VL__ 1
609-
// AVX512FP16NOAVX512VL-NOT: #define __EVEX256__ 1
604+
// AVX512FP16NOAVX512VL: #define __AVX512FP16__ 1
610605
// AVX512FP16NOAVX512VL: #define __EVEX512__ 1
611606

612607
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512fp16 -mno-avx512bw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512FP16NOAVX512BW %s
613608

614609
// AVX512FP16NOAVX512BW-NOT: #define __AVX512BW__ 1
615610
// AVX512FP16NOAVX512BW-NOT: #define __AVX512FP16__ 1
616-
// AVX512FP16NOAVX512BW: #define __EVEX256__ 1
617611
// AVX512FP16NOAVX512BW: #define __EVEX512__ 1
618612

619613
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512fp16 -mno-avx512dq -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512FP16NOAVX512DQ %s
620614

621615
// AVX512FP16NOAVX512DQ-NOT: #define __AVX512DQ__ 1
622-
// AVX512FP16NOAVX512DQ-NOT: #define __AVX512FP16__ 1
623-
// AVX512FP16NOAVX512DQ: #define __EVEX256__ 1
616+
// AVX512FP16NOAVX512DQ: #define __AVX512FP16__ 1
624617
// AVX512FP16NOAVX512DQ: #define __EVEX512__ 1
625618

626619
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512f -mno-avx512f -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOEVEX512 %s

‎llvm/include/llvm/ADT/AddressRanges.h

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -97,10 +97,8 @@ template <typename T> class AddressRangesBase {
9797
if (Start >= End)
9898
return Ranges.end();
9999

100-
auto It =
101-
std::partition_point(Ranges.begin(), Ranges.end(), [=](const T &R) {
102-
return AddressRange(R).start() <= Start;
103-
});
100+
auto It = llvm::partition_point(
101+
Ranges, [=](const T &R) { return AddressRange(R).start() <= Start; });
104102

105103
if (It == Ranges.begin())
106104
return Ranges.end();
@@ -169,10 +167,10 @@ class AddressRangesMap : public AddressRangesBase<AddressRangeValuePair> {
169167
return;
170168

171169
// Search for range which is less than or equal incoming Range.
172-
auto It = std::partition_point(Ranges.begin(), Ranges.end(),
173-
[=](const AddressRangeValuePair &R) {
174-
return R.Range.start() <= Range.start();
175-
});
170+
auto It =
171+
llvm::partition_point(Ranges, [=](const AddressRangeValuePair &R) {
172+
return R.Range.start() <= Range.start();
173+
});
176174

177175
if (It != Ranges.begin())
178176
It--;

‎llvm/lib/Analysis/ScalarEvolution.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -116,6 +116,7 @@
116116
#include "llvm/Support/Compiler.h"
117117
#include "llvm/Support/Debug.h"
118118
#include "llvm/Support/ErrorHandling.h"
119+
#include "llvm/Support/InterleavedRange.h"
119120
#include "llvm/Support/KnownBits.h"
120121
#include "llvm/Support/SaveAndRestore.h"
121122
#include "llvm/Support/raw_ostream.h"
@@ -349,11 +350,9 @@ void SCEV::print(raw_ostream &OS) const {
349350
default:
350351
llvm_unreachable("There are no other nary expression types.");
351352
}
352-
OS << "(";
353-
ListSeparator LS(OpStr);
354-
for (const SCEV *Op : NAry->operands())
355-
OS << LS << *Op;
356-
OS << ")";
353+
OS << "("
354+
<< llvm::interleaved(llvm::make_pointee_range(NAry->operands()), OpStr)
355+
<< ")";
357356
switch (NAry->getSCEVType()) {
358357
case scAddExpr:
359358
case scMulExpr:

‎llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp

Lines changed: 22 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1046,17 +1046,16 @@ class MFMAExpInterleaveOpt final : public IGLPStrategy {
10461046
if (!SyncPipe.size())
10471047
return false;
10481048

1049-
auto SuccSize = std::count_if(
1050-
SU->Succs.begin(), SU->Succs.end(),
1051-
[](const SDep &Succ) { return Succ.getKind() == SDep::Data; });
1049+
auto SuccSize = llvm::count_if(SU->Succs, [](const SDep &Succ) {
1050+
return Succ.getKind() == SDep::Data;
1051+
});
10521052
if (SuccSize >= Size)
10531053
return false;
10541054

10551055
if (HasIntermediary) {
10561056
for (auto Succ : SU->Succs) {
1057-
auto SuccSize = std::count_if(
1058-
Succ.getSUnit()->Succs.begin(), Succ.getSUnit()->Succs.end(),
1059-
[](const SDep &SuccSucc) {
1057+
auto SuccSize =
1058+
llvm::count_if(Succ.getSUnit()->Succs, [](const SDep &SuccSucc) {
10601059
return SuccSucc.getKind() == SDep::Data;
10611060
});
10621061
if (SuccSize >= Size)
@@ -1087,17 +1086,16 @@ class MFMAExpInterleaveOpt final : public IGLPStrategy {
10871086
if (!SyncPipe.size())
10881087
return false;
10891088

1090-
auto SuccSize = std::count_if(
1091-
SU->Succs.begin(), SU->Succs.end(),
1092-
[](const SDep &Succ) { return Succ.getKind() == SDep::Data; });
1089+
auto SuccSize = llvm::count_if(SU->Succs, [](const SDep &Succ) {
1090+
return Succ.getKind() == SDep::Data;
1091+
});
10931092
if (SuccSize >= Size)
10941093
return true;
10951094

10961095
if (HasIntermediary) {
10971096
for (auto Succ : SU->Succs) {
1098-
auto SuccSize = std::count_if(
1099-
Succ.getSUnit()->Succs.begin(), Succ.getSUnit()->Succs.end(),
1100-
[](const SDep &SuccSucc) {
1097+
auto SuccSize =
1098+
llvm::count_if(Succ.getSUnit()->Succs, [](const SDep &SuccSucc) {
11011099
return SuccSucc.getKind() == SDep::Data;
11021100
});
11031101
if (SuccSize >= Size)
@@ -1474,18 +1472,17 @@ bool MFMAExpInterleaveOpt::analyzeDAG(const SIInstrInfo *TII) {
14741472
MFMAChainLength = MFMAPipeCount / MFMAChains;
14751473

14761474
// The number of bit pack operations that depend on a single V_EXP
1477-
unsigned PackSuccCount = std::count_if(
1478-
PackSUs.begin(), PackSUs.end(), [this, &TempExp](SUnit *VPack) {
1475+
unsigned PackSuccCount =
1476+
llvm::count_if(PackSUs, [this, &TempExp](SUnit *VPack) {
14791477
return DAG->IsReachable(VPack, *TempExp);
14801478
});
14811479

14821480
// The number of bit pack operations an MFMA depends on
14831481
unsigned PackPredCount =
1484-
std::count_if((*TempMFMA)->Preds.begin(), (*TempMFMA)->Preds.end(),
1485-
[&isBitPack](SDep &Pred) {
1486-
auto Opc = Pred.getSUnit()->getInstr()->getOpcode();
1487-
return isBitPack(Opc);
1488-
});
1482+
llvm::count_if((*TempMFMA)->Preds, [&isBitPack](SDep &Pred) {
1483+
auto Opc = Pred.getSUnit()->getInstr()->getOpcode();
1484+
return isBitPack(Opc);
1485+
});
14891486

14901487
auto *PackPred = llvm::find_if((*TempMFMA)->Preds, [&isBitPack](SDep &Pred) {
14911488
auto Opc = Pred.getSUnit()->getInstr()->getOpcode();
@@ -1499,20 +1496,18 @@ bool MFMAExpInterleaveOpt::analyzeDAG(const SIInstrInfo *TII) {
14991496
ExpRequirement = 0;
15001497
// How many MFMAs depend on a single bit pack operation
15011498
MFMAEnablement =
1502-
std::count_if(PackPred->getSUnit()->Succs.begin(),
1503-
PackPred->getSUnit()->Succs.end(), [&TII](SDep &Succ) {
1504-
return TII->isMFMAorWMMA(*Succ.getSUnit()->getInstr());
1505-
});
1499+
llvm::count_if(PackPred->getSUnit()->Succs, [&TII](SDep &Succ) {
1500+
return TII->isMFMAorWMMA(*Succ.getSUnit()->getInstr());
1501+
});
15061502

15071503
// The number of MFMAs that depend on a single V_EXP
15081504
MFMAEnablement *= PackSuccCount;
15091505

15101506
// The number of V_EXPs required to resolve all dependencies for an MFMA
15111507
ExpRequirement =
1512-
std::count_if(ExpPipeCands.begin(), ExpPipeCands.end(),
1513-
[this, &PackPred](SUnit *ExpBase) {
1514-
return DAG->IsReachable(PackPred->getSUnit(), ExpBase);
1515-
});
1508+
llvm::count_if(ExpPipeCands, [this, &PackPred](SUnit *ExpBase) {
1509+
return DAG->IsReachable(PackPred->getSUnit(), ExpBase);
1510+
});
15161511

15171512
ExpRequirement *= PackPredCount;
15181513
return true;

‎llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2868,8 +2868,11 @@ bool RISCVTTIImpl::isProfitableToSinkOperands(
28682868
if (!Op || any_of(Ops, [&](Use *U) { return U->get() == Op; }))
28692869
continue;
28702870

2871-
// We are looking for a splat that can be sunk.
2872-
if (!match(Op, m_Shuffle(m_InsertElt(m_Undef(), m_Value(), m_ZeroInt()),
2871+
// We are looking for a splat/vp.splat that can be sunk.
2872+
bool IsVPSplat = match(Op, m_Intrinsic<Intrinsic::experimental_vp_splat>(
2873+
m_Value(), m_Value(), m_Value()));
2874+
if (!IsVPSplat &&
2875+
!match(Op, m_Shuffle(m_InsertElt(m_Undef(), m_Value(), m_ZeroInt()),
28732876
m_Undef(), m_ZeroMask())))
28742877
continue;
28752878

@@ -2885,12 +2888,17 @@ bool RISCVTTIImpl::isProfitableToSinkOperands(
28852888
return false;
28862889
}
28872890

2888-
Use *InsertEltUse = &Op->getOperandUse(0);
28892891
// Sink any fpexts since they might be used in a widening fp pattern.
2890-
auto *InsertElt = cast<InsertElementInst>(InsertEltUse);
2891-
if (isa<FPExtInst>(InsertElt->getOperand(1)))
2892-
Ops.push_back(&InsertElt->getOperandUse(1));
2893-
Ops.push_back(InsertEltUse);
2892+
if (IsVPSplat) {
2893+
if (isa<FPExtInst>(Op->getOperand(0)))
2894+
Ops.push_back(&Op->getOperandUse(0));
2895+
} else {
2896+
Use *InsertEltUse = &Op->getOperandUse(0);
2897+
auto *InsertElt = cast<InsertElementInst>(InsertEltUse);
2898+
if (isa<FPExtInst>(InsertElt->getOperand(1)))
2899+
Ops.push_back(&InsertElt->getOperandUse(1));
2900+
Ops.push_back(InsertEltUse);
2901+
}
28942902
Ops.push_back(&OpIdx.value());
28952903
}
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return true;

‎llvm/lib/Target/X86/X86.td

Lines changed: 2 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -166,14 +166,9 @@ def FeatureVP2INTERSECT : SubtargetFeature<"avx512vp2intersect",
166166
"HasVP2INTERSECT", "true",
167167
"Enable AVX-512 vp2intersect",
168168
[FeatureAVX512]>;
169-
// FIXME: FP16 scalar intrinsics use the type v8f16, which is supposed to be
170-
// guarded under condition hasVLX. So we imply it in FeatureFP16 currently.
171-
// FIXME: FP16 conversion between f16 and i64 customize type v8i64, which is
172-
// supposed to be guarded under condition hasDQI. So we imply it in FeatureFP16
173-
// currently.
174169
def FeatureFP16 : SubtargetFeature<"avx512fp16", "HasFP16", "true",
175170
"Support 16-bit floating point",
176-
[FeatureBWI, FeatureVLX, FeatureDQI]>;
171+
[FeatureBWI]>;
177172
def FeatureAVXVNNIINT8 : SubtargetFeature<"avxvnniint8",
178173
"HasAVXVNNIINT8", "true",
179174
"Enable AVX-VNNI-INT8",
@@ -338,7 +333,7 @@ def FeatureAVX10_1 : SubtargetFeature<"avx10.1-256", "HasAVX10_1", "true",
338333
"Support AVX10.1 up to 256-bit instruction",
339334
[FeatureCDI, FeatureVBMI, FeatureIFMA, FeatureVNNI,
340335
FeatureBF16, FeatureVPOPCNTDQ, FeatureVBMI2, FeatureBITALG,
341-
FeatureFP16]>;
336+
FeatureFP16, FeatureVLX, FeatureDQI]>;
342337
def FeatureAVX10_1_512 : SubtargetFeature<"avx10.1-512", "HasAVX10_1_512", "true",
343338
"Support AVX10.1 up to 512-bit instruction",
344339
[FeatureAVX10_1, FeatureEVEX512]>;

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