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masahir0ystorulf
masahir0y
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storulf
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mmc: tmio: move tmio_mmc_set_clock() to platform hook
tmio_mmc_set_clock() is full of quirks because different SoC vendors extended this in different ways. The original IP defines the divisor range 1/2 ... 1/512. bit 7 is set: 1/512 bit 6 is set: 1/256 ... bit 0 is set: 1/4 all bits clear: 1/2 It is platform-dependent how to achieve the 1/1 clock. I guess the TMIO-MFD variant uses the clock selector outside of this IP, as far as I see tmio_core_mmc_clk_div() in drivers/mfd/tmio_core.c I guess bit[7:0]=0xff is Renesas-specific extension. Socionext (and Panasonic) uses bit 10 (CLKSEL) for 1/1. Also, newer versions of UniPhier SoC variants use bit 16 for 1/1024. host->clk_update() is only used by the Renesas variants, whereas host->set_clk_div() is only used by the TMIO-MFD variants. To cope with this mess, promote tmio_mmc_set_clock() to a new platform hook ->set_clock(), and melt the old two hooks into it. Signed-off-by: Masahiro Yamada <[email protected]> Reviewed-by: Wolfram Sang <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
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‎drivers/mmc/host/renesas_sdhi_core.c

Lines changed: 61 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -152,6 +152,66 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
152152
return ret == 0 ? best_freq : clk_get_rate(priv->clk);
153153
}
154154

155+
static void renesas_sdhi_clk_start(struct tmio_mmc_host *host)
156+
{
157+
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
158+
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
159+
160+
/* HW engineers overrode docs: no sleep needed on R-Car2+ */
161+
if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
162+
usleep_range(10000, 11000);
163+
}
164+
165+
static void renesas_sdhi_clk_stop(struct tmio_mmc_host *host)
166+
{
167+
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
168+
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
169+
170+
/* HW engineers overrode docs: no sleep needed on R-Car2+ */
171+
if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
172+
usleep_range(10000, 11000);
173+
}
174+
175+
static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
176+
unsigned int new_clock)
177+
{
178+
u32 clk = 0, clock;
179+
180+
if (new_clock == 0) {
181+
renesas_sdhi_clk_stop(host);
182+
return;
183+
}
184+
/*
185+
* Both HS400 and HS200/SD104 set 200MHz, but some devices need to
186+
* set 400MHz to distinguish the CPG settings in HS400.
187+
*/
188+
if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
189+
host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400 &&
190+
new_clock == 200000000)
191+
new_clock = 400000000;
192+
193+
clock = renesas_sdhi_clk_update(host, new_clock) / 512;
194+
195+
for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
196+
clock <<= 1;
197+
198+
/* 1/1 clock is option */
199+
if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
200+
if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
201+
clk |= 0xff;
202+
else
203+
clk &= ~0xff;
204+
}
205+
206+
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
207+
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
208+
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
209+
if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
210+
usleep_range(10000, 11000);
211+
212+
renesas_sdhi_clk_start(host);
213+
}
214+
155215
static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
156216
{
157217
struct renesas_sdhi *priv = host_to_priv(host);
@@ -617,8 +677,8 @@ int renesas_sdhi_probe(struct platform_device *pdev,
617677

618678
host->write16_hook = renesas_sdhi_write16_hook;
619679
host->clk_enable = renesas_sdhi_clk_enable;
620-
host->clk_update = renesas_sdhi_clk_update;
621680
host->clk_disable = renesas_sdhi_clk_disable;
681+
host->set_clock = renesas_sdhi_set_clock;
622682
host->multi_io_quirk = renesas_sdhi_multi_io_quirk;
623683
host->dma_ops = dma_ops;
624684

‎drivers/mmc/host/tmio_mmc.c

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
1010
* Copyright (C) 2004 Ian Molton
1111
*/
1212

13+
#include <linux/delay.h>
1314
#include <linux/device.h>
1415
#include <linux/mfd/core.h>
1516
#include <linux/mfd/tmio.h>
@@ -20,6 +21,52 @@
2021

2122
#include "tmio_mmc.h"
2223

24+
static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
25+
{
26+
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
27+
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
28+
29+
usleep_range(10000, 11000);
30+
sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
31+
usleep_range(10000, 11000);
32+
}
33+
34+
static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
35+
{
36+
sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
37+
usleep_range(10000, 11000);
38+
39+
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
40+
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
41+
42+
usleep_range(10000, 11000);
43+
}
44+
45+
static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
46+
unsigned int new_clock)
47+
{
48+
u32 clk = 0, clock;
49+
50+
if (new_clock == 0) {
51+
tmio_mmc_clk_stop(host);
52+
return;
53+
}
54+
55+
clock = host->mmc->f_min;
56+
57+
for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
58+
clock <<= 1;
59+
60+
host->pdata->set_clk_div(host->pdev, (clk >> 22) & 1);
61+
62+
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
63+
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
64+
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
65+
usleep_range(10000, 11000);
66+
67+
tmio_mmc_clk_start(host);
68+
}
69+
2370
#ifdef CONFIG_PM_SLEEP
2471
static int tmio_mmc_suspend(struct device *dev)
2572
{
@@ -97,6 +144,7 @@ static int tmio_mmc_probe(struct platform_device *pdev)
97144

98145
/* SD control register space size is 0x200, 0x400 for bus_shift=1 */
99146
host->bus_shift = resource_size(res) >> 10;
147+
host->set_clock = tmio_mmc_set_clock;
100148

101149
host->mmc->f_max = pdata->hclk;
102150
host->mmc->f_min = pdata->hclk / 512;

‎drivers/mmc/host/tmio_mmc.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -129,7 +129,6 @@ struct tmio_mmc_host {
129129

130130
/* Callbacks for clock / power control */
131131
void (*set_pwr)(struct platform_device *host, int state);
132-
void (*set_clk_div)(struct platform_device *host, int state);
133132

134133
/* pio related stuff */
135134
struct scatterlist *sg_ptr;
@@ -166,10 +165,9 @@ struct tmio_mmc_host {
166165

167166
/* Mandatory callback */
168167
int (*clk_enable)(struct tmio_mmc_host *host);
168+
void (*set_clock)(struct tmio_mmc_host *host, unsigned int clock);
169169

170170
/* Optional callbacks */
171-
unsigned int (*clk_update)(struct tmio_mmc_host *host,
172-
unsigned int new_clock);
173171
void (*clk_disable)(struct tmio_mmc_host *host);
174172
int (*multi_io_quirk)(struct mmc_card *card,
175173
unsigned int direction, int blk_size);

‎drivers/mmc/host/tmio_mmc_core.c

Lines changed: 7 additions & 85 deletions
Original file line numberDiff line numberDiff line change
@@ -157,83 +157,6 @@ static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
157157
}
158158
}
159159

160-
static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
161-
{
162-
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
163-
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
164-
165-
/* HW engineers overrode docs: no sleep needed on R-Car2+ */
166-
if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
167-
usleep_range(10000, 11000);
168-
169-
if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
170-
sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
171-
usleep_range(10000, 11000);
172-
}
173-
}
174-
175-
static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
176-
{
177-
if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
178-
sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
179-
usleep_range(10000, 11000);
180-
}
181-
182-
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
183-
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
184-
185-
/* HW engineers overrode docs: no sleep needed on R-Car2+ */
186-
if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
187-
usleep_range(10000, 11000);
188-
}
189-
190-
static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
191-
unsigned int new_clock)
192-
{
193-
u32 clk = 0, clock;
194-
195-
if (new_clock == 0) {
196-
tmio_mmc_clk_stop(host);
197-
return;
198-
}
199-
/*
200-
* Both HS400 and HS200/SD104 set 200MHz, but some devices need to
201-
* set 400MHz to distinguish the CPG settings in HS400.
202-
*/
203-
if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
204-
host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400 &&
205-
new_clock == 200000000)
206-
new_clock = 400000000;
207-
208-
if (host->clk_update)
209-
clock = host->clk_update(host, new_clock) / 512;
210-
else
211-
clock = host->mmc->f_min;
212-
213-
for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
214-
clock <<= 1;
215-
216-
/* 1/1 clock is option */
217-
if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) &&
218-
((clk >> 22) & 0x1)) {
219-
if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
220-
clk |= 0xff;
221-
else
222-
clk &= ~0xff;
223-
}
224-
225-
if (host->set_clk_div)
226-
host->set_clk_div(host->pdev, (clk >> 22) & 1);
227-
228-
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
229-
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
230-
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
231-
if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
232-
usleep_range(10000, 11000);
233-
234-
tmio_mmc_clk_start(host);
235-
}
236-
237160
static void tmio_mmc_reset(struct tmio_mmc_host *host)
238161
{
239162
/* FIXME - should we set stop clock reg here */
@@ -1040,15 +963,15 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1040963
switch (ios->power_mode) {
1041964
case MMC_POWER_OFF:
1042965
tmio_mmc_power_off(host);
1043-
tmio_mmc_set_clock(host, 0);
966+
host->set_clock(host, 0);
1044967
break;
1045968
case MMC_POWER_UP:
1046969
tmio_mmc_power_on(host, ios->vdd);
1047-
tmio_mmc_set_clock(host, ios->clock);
970+
host->set_clock(host, ios->clock);
1048971
tmio_mmc_set_bus_width(host, ios->bus_width);
1049972
break;
1050973
case MMC_POWER_ON:
1051-
tmio_mmc_set_clock(host, ios->clock);
974+
host->set_clock(host, ios->clock);
1052975
tmio_mmc_set_bus_width(host, ios->bus_width);
1053976
break;
1054977
}
@@ -1234,7 +1157,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
12341157
int ret;
12351158

12361159
/*
1237-
* Check the sanity of mmc->f_min to prevent tmio_mmc_set_clock() from
1160+
* Check the sanity of mmc->f_min to prevent host->set_clock() from
12381161
* looping forever...
12391162
*/
12401163
if (mmc->f_min == 0)
@@ -1244,7 +1167,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
12441167
_host->write16_hook = NULL;
12451168

12461169
_host->set_pwr = pdata->set_pwr;
1247-
_host->set_clk_div = pdata->set_clk_div;
12481170

12491171
ret = tmio_mmc_init_ocr(_host);
12501172
if (ret < 0)
@@ -1307,7 +1229,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
13071229
if (pdata->flags & TMIO_MMC_SDIO_IRQ)
13081230
_host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
13091231

1310-
tmio_mmc_set_clock(_host, 0);
1232+
_host->set_clock(_host, 0);
13111233
tmio_mmc_reset(_host);
13121234

13131235
_host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK);
@@ -1391,7 +1313,7 @@ int tmio_mmc_host_runtime_suspend(struct device *dev)
13911313
tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
13921314

13931315
if (host->clk_cache)
1394-
tmio_mmc_set_clock(host, 0);
1316+
host->set_clock(host, 0);
13951317

13961318
tmio_mmc_clk_disable(host);
13971319

@@ -1412,7 +1334,7 @@ int tmio_mmc_host_runtime_resume(struct device *dev)
14121334
tmio_mmc_clk_enable(host);
14131335

14141336
if (host->clk_cache)
1415-
tmio_mmc_set_clock(host, host->clk_cache);
1337+
host->set_clock(host, host->clk_cache);
14161338

14171339
if (host->native_hotplug)
14181340
tmio_mmc_enable_mmc_irqs(host,

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