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chenhuacaichenhuacai
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LoongArch: Add exception/interrupt handling
Add the exception and interrupt handling machanism for basic LoongArch support. Reviewed-by: WANG Xuerui <[email protected]> Reviewed-by: Jiaxun Yang <[email protected]> Signed-off-by: Huacai Chen <[email protected]>
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‎arch/loongarch/include/asm/branch.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_BRANCH_H
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#define _ASM_BRANCH_H
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#include <asm/ptrace.h>
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static inline unsigned long exception_era(struct pt_regs *regs)
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{
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return regs->csr_era;
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}
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static inline int compute_return_era(struct pt_regs *regs)
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{
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regs->csr_era += 4;
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return 0;
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}
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#endif /* _ASM_BRANCH_H */

‎arch/loongarch/include/asm/bug.h

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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_BUG_H
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#define __ASM_BUG_H
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#include <linux/compiler.h>
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#ifdef CONFIG_BUG
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#include <asm/break.h>
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static inline void __noreturn BUG(void)
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{
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__asm__ __volatile__("break %0" : : "i" (BRK_BUG));
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unreachable();
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}
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#define HAVE_ARCH_BUG
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#endif
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#include <asm-generic/bug.h>
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#endif /* __ASM_BUG_H */

‎arch/loongarch/include/asm/entry-common.h

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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef ARCH_LOONGARCH_ENTRY_COMMON_H
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#define ARCH_LOONGARCH_ENTRY_COMMON_H
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#include <linux/sched.h>
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#include <linux/processor.h>
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static inline bool on_thread_stack(void)
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{
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return !(((unsigned long)(current->stack) ^ current_stack_pointer) & ~(THREAD_SIZE - 1));
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}
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#endif

‎arch/loongarch/include/asm/hardirq.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_HARDIRQ_H
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#define _ASM_HARDIRQ_H
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#include <linux/cache.h>
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#include <linux/threads.h>
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#include <linux/irq.h>
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extern void ack_bad_irq(unsigned int irq);
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#define ack_bad_irq ack_bad_irq
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#define NR_IPI 2
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typedef struct {
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unsigned int ipi_irqs[NR_IPI];
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unsigned int __softirq_pending;
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} ____cacheline_aligned irq_cpustat_t;
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DECLARE_PER_CPU_ALIGNED(irq_cpustat_t, irq_stat);
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#endif /* _ASM_HARDIRQ_H */

‎arch/loongarch/include/asm/hw_irq.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef __ASM_HW_IRQ_H
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#define __ASM_HW_IRQ_H
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#include <linux/atomic.h>
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extern atomic_t irq_err_count;
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/*
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* interrupt-retrigger: NOP for now. This may not be appropriate for all
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* machines, we'll see ...
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*/
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#endif /* __ASM_HW_IRQ_H */

‎arch/loongarch/include/asm/irq.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_IRQ_H
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#define _ASM_IRQ_H
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#include <linux/irqdomain.h>
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#include <linux/irqreturn.h>
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#define IRQ_STACK_SIZE THREAD_SIZE
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#define IRQ_STACK_START (IRQ_STACK_SIZE - 16)
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DECLARE_PER_CPU(unsigned long, irq_stack);
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/*
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* The highest address on the IRQ stack contains a dummy frame which is
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* structured as follows:
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*
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* top ------------
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* | task sp | <- irq_stack[cpu] + IRQ_STACK_START
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* ------------
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* | | <- First frame of IRQ context
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* ------------
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*
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* task sp holds a copy of the task stack pointer where the struct pt_regs
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* from exception entry can be found.
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*/
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static inline bool on_irq_stack(int cpu, unsigned long sp)
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{
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unsigned long low = per_cpu(irq_stack, cpu);
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unsigned long high = low + IRQ_STACK_SIZE;
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return (low <= sp && sp <= high);
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}
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int get_ipi_irq(void);
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int get_pmc_irq(void);
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int get_timer_irq(void);
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void spurious_interrupt(void);
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#define NR_IRQS_LEGACY 16
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#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
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void arch_trigger_cpumask_backtrace(const struct cpumask *mask, bool exclude_self);
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#define MAX_IO_PICS 2
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#define NR_IRQS (64 + (256 * MAX_IO_PICS))
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#define CORES_PER_EIO_NODE 4
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#define LOONGSON_CPU_UART0_VEC 10 /* CPU UART0 */
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#define LOONGSON_CPU_THSENS_VEC 14 /* CPU Thsens */
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#define LOONGSON_CPU_HT0_VEC 16 /* CPU HT0 irq vector base number */
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#define LOONGSON_CPU_HT1_VEC 24 /* CPU HT1 irq vector base number */
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/* IRQ number definitions */
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#define LOONGSON_LPC_IRQ_BASE 0
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#define LOONGSON_LPC_LAST_IRQ (LOONGSON_LPC_IRQ_BASE + 15)
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#define LOONGSON_CPU_IRQ_BASE 16
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#define LOONGSON_CPU_LAST_IRQ (LOONGSON_CPU_IRQ_BASE + 14)
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#define LOONGSON_PCH_IRQ_BASE 64
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#define LOONGSON_PCH_ACPI_IRQ (LOONGSON_PCH_IRQ_BASE + 47)
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#define LOONGSON_PCH_LAST_IRQ (LOONGSON_PCH_IRQ_BASE + 64 - 1)
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#define LOONGSON_MSI_IRQ_BASE (LOONGSON_PCH_IRQ_BASE + 64)
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#define LOONGSON_MSI_LAST_IRQ (LOONGSON_PCH_IRQ_BASE + 256 - 1)
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#define GSI_MIN_LPC_IRQ LOONGSON_LPC_IRQ_BASE
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#define GSI_MAX_LPC_IRQ (LOONGSON_LPC_IRQ_BASE + 16 - 1)
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#define GSI_MIN_CPU_IRQ LOONGSON_CPU_IRQ_BASE
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#define GSI_MAX_CPU_IRQ (LOONGSON_CPU_IRQ_BASE + 48 - 1)
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#define GSI_MIN_PCH_IRQ LOONGSON_PCH_IRQ_BASE
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#define GSI_MAX_PCH_IRQ (LOONGSON_PCH_IRQ_BASE + 256 - 1)
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extern int find_pch_pic(u32 gsi);
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extern int eiointc_get_node(int id);
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static inline void eiointc_enable(void)
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{
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uint64_t misc;
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misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
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misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
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iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
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}
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struct acpi_madt_lio_pic;
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struct acpi_madt_eio_pic;
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struct acpi_madt_ht_pic;
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struct acpi_madt_bio_pic;
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struct acpi_madt_msi_pic;
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struct acpi_madt_lpc_pic;
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struct irq_domain *loongarch_cpu_irq_init(void);
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struct irq_domain *liointc_acpi_init(struct irq_domain *parent,
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struct acpi_madt_lio_pic *acpi_liointc);
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struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
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struct acpi_madt_eio_pic *acpi_eiointc);
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struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
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struct acpi_madt_ht_pic *acpi_htvec);
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struct irq_domain *pch_lpc_acpi_init(struct irq_domain *parent,
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struct acpi_madt_lpc_pic *acpi_pchlpc);
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struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
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struct acpi_madt_msi_pic *acpi_pchmsi);
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struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent,
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struct acpi_madt_bio_pic *acpi_pchpic);
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extern struct acpi_madt_lio_pic *acpi_liointc;
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extern struct acpi_madt_eio_pic *acpi_eiointc[MAX_IO_PICS];
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extern struct acpi_madt_ht_pic *acpi_htintc;
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extern struct acpi_madt_lpc_pic *acpi_pchlpc;
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extern struct acpi_madt_msi_pic *acpi_pchmsi[MAX_IO_PICS];
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extern struct acpi_madt_bio_pic *acpi_pchpic[MAX_IO_PICS];
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extern struct irq_domain *cpu_domain;
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extern struct irq_domain *liointc_domain;
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extern struct irq_domain *pch_lpc_domain;
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extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];
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extern struct irq_domain *pch_pic_domain[MAX_IO_PICS];
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#include <asm-generic/irq.h>
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#endif /* _ASM_IRQ_H */

‎arch/loongarch/include/asm/irq_regs.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef __ASM_IRQ_REGS_H
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#define __ASM_IRQ_REGS_H
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#define ARCH_HAS_OWN_IRQ_REGS
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#include <linux/thread_info.h>
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static inline struct pt_regs *get_irq_regs(void)
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{
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return current_thread_info()->regs;
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}
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static inline struct pt_regs *set_irq_regs(struct pt_regs *new_regs)
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{
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struct pt_regs *old_regs;
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old_regs = get_irq_regs();
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current_thread_info()->regs = new_regs;
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return old_regs;
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}
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#endif /* __ASM_IRQ_REGS_H */

‎arch/loongarch/include/asm/irqflags.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_IRQFLAGS_H
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#define _ASM_IRQFLAGS_H
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#ifndef __ASSEMBLY__
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#include <linux/compiler.h>
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#include <linux/stringify.h>
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#include <asm/compiler.h>
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#include <asm/loongarch.h>
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static inline void arch_local_irq_enable(void)
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{
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u32 flags = CSR_CRMD_IE;
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__asm__ __volatile__(
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"csrxchg %[val], %[mask], %[reg]\n\t"
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: [val] "+r" (flags)
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: [mask] "r" (CSR_CRMD_IE), [reg] "i" (LOONGARCH_CSR_CRMD)
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: "memory");
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}
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static inline void arch_local_irq_disable(void)
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{
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u32 flags = 0;
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__asm__ __volatile__(
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"csrxchg %[val], %[mask], %[reg]\n\t"
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: [val] "+r" (flags)
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: [mask] "r" (CSR_CRMD_IE), [reg] "i" (LOONGARCH_CSR_CRMD)
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: "memory");
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}
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static inline unsigned long arch_local_irq_save(void)
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{
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u32 flags = 0;
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__asm__ __volatile__(
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"csrxchg %[val], %[mask], %[reg]\n\t"
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: [val] "+r" (flags)
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: [mask] "r" (CSR_CRMD_IE), [reg] "i" (LOONGARCH_CSR_CRMD)
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: "memory");
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return flags;
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}
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static inline void arch_local_irq_restore(unsigned long flags)
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{
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__asm__ __volatile__(
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"csrxchg %[val], %[mask], %[reg]\n\t"
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: [val] "+r" (flags)
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: [mask] "r" (CSR_CRMD_IE), [reg] "i" (LOONGARCH_CSR_CRMD)
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: "memory");
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}
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static inline unsigned long arch_local_save_flags(void)
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{
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u32 flags;
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__asm__ __volatile__(
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"csrrd %[val], %[reg]\n\t"
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: [val] "=r" (flags)
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: [reg] "i" (LOONGARCH_CSR_CRMD)
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: "memory");
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return flags;
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}
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static inline int arch_irqs_disabled_flags(unsigned long flags)
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{
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return !(flags & CSR_CRMD_IE);
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}
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static inline int arch_irqs_disabled(void)
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{
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return arch_irqs_disabled_flags(arch_local_save_flags());
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}
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#endif /* #ifndef __ASSEMBLY__ */
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#endif /* _ASM_IRQFLAGS_H */

‎arch/loongarch/include/asm/kdebug.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_LOONGARCH_KDEBUG_H
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#define _ASM_LOONGARCH_KDEBUG_H
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#include <linux/notifier.h>
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enum die_val {
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DIE_OOPS = 1,
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DIE_RI,
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DIE_FP,
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DIE_SIMD,
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DIE_TRAP,
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DIE_PAGE_FAULT,
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DIE_BREAK,
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DIE_SSTEPBP,
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DIE_UPROBE,
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DIE_UPROBE_XOL,
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};
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#endif /* _ASM_LOONGARCH_KDEBUG_H */

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