@@ -725,3 +725,74 @@ const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = {
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.ctrl = exynosautov9_pin_ctrl ,
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.num_ctrl = ARRAY_SIZE (exynosautov9_pin_ctrl ),
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};
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+
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+ /*
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+ * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three
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+ * gpio/pin-mux/pinconfig controllers.
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+ */
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+
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+ /* pin banks of FSD pin-controller 0 (FSYS) */
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+ static const struct samsung_pin_bank_data fsd_pin_banks0 [] __initconst = {
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+ EXYNOS850_PIN_BANK_EINTG (7 , 0x00 , "gpf0" , 0x00 ),
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+ EXYNOS850_PIN_BANK_EINTG (8 , 0x20 , "gpf1" , 0x04 ),
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+ EXYNOS850_PIN_BANK_EINTG (3 , 0x40 , "gpf6" , 0x08 ),
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+ EXYNOS850_PIN_BANK_EINTG (2 , 0x60 , "gpf4" , 0x0c ),
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+ EXYNOS850_PIN_BANK_EINTG (6 , 0x80 , "gpf5" , 0x10 ),
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+ };
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+
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+ /* pin banks of FSD pin-controller 1 (PERIC) */
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+ static const struct samsung_pin_bank_data fsd_pin_banks1 [] __initconst = {
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+ EXYNOS850_PIN_BANK_EINTG (4 , 0x000 , "gpc8" , 0x00 ),
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+ EXYNOS850_PIN_BANK_EINTG (7 , 0x020 , "gpf2" , 0x04 ),
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+ EXYNOS850_PIN_BANK_EINTG (8 , 0x040 , "gpf3" , 0x08 ),
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+ EXYNOS850_PIN_BANK_EINTG (8 , 0x060 , "gpd0" , 0x0c ),
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+ EXYNOS850_PIN_BANK_EINTG (8 , 0x080 , "gpb0" , 0x10 ),
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+ EXYNOS850_PIN_BANK_EINTG (8 , 0x0a0 , "gpb1" , 0x14 ),
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+ EXYNOS850_PIN_BANK_EINTG (8 , 0x0c0 , "gpb4" , 0x18 ),
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+ EXYNOS850_PIN_BANK_EINTG (4 , 0x0e0 , "gpb5" , 0x1c ),
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+ EXYNOS850_PIN_BANK_EINTG (8 , 0x100 , "gpb6" , 0x20 ),
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+ EXYNOS850_PIN_BANK_EINTG (8 , 0x120 , "gpb7" , 0x24 ),
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+ EXYNOS850_PIN_BANK_EINTG (5 , 0x140 , "gpd1" , 0x28 ),
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+ EXYNOS850_PIN_BANK_EINTG (5 , 0x160 , "gpd2" , 0x2c ),
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+ EXYNOS850_PIN_BANK_EINTG (7 , 0x180 , "gpd3" , 0x30 ),
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+ EXYNOS850_PIN_BANK_EINTG (8 , 0x1a0 , "gpg0" , 0x34 ),
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+ EXYNOS850_PIN_BANK_EINTG (8 , 0x1c0 , "gpg1" , 0x38 ),
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+ EXYNOS850_PIN_BANK_EINTG (8 , 0x1e0 , "gpg2" , 0x3c ),
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+ EXYNOS850_PIN_BANK_EINTG (8 , 0x200 , "gpg3" , 0x40 ),
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+ EXYNOS850_PIN_BANK_EINTG (8 , 0x220 , "gpg4" , 0x44 ),
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+ EXYNOS850_PIN_BANK_EINTG (8 , 0x240 , "gpg5" , 0x48 ),
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+ EXYNOS850_PIN_BANK_EINTG (8 , 0x260 , "gpg6" , 0x4c ),
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+ EXYNOS850_PIN_BANK_EINTG (8 , 0x280 , "gpg7" , 0x50 ),
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+ };
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+
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+ /* pin banks of FSD pin-controller 2 (PMU) */
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+ static const struct samsung_pin_bank_data fsd_pin_banks2 [] __initconst = {
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+ EXYNOS850_PIN_BANK_EINTN (3 , 0x00 , "gpq0" ),
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+ };
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+
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+ const struct samsung_pin_ctrl fsd_pin_ctrl [] __initconst = {
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+ {
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+ /* pin-controller instance 0 FSYS0 data */
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+ .pin_banks = fsd_pin_banks0 ,
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+ .nr_banks = ARRAY_SIZE (fsd_pin_banks0 ),
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+ .eint_gpio_init = exynos_eint_gpio_init ,
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+ .suspend = exynos_pinctrl_suspend ,
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+ .resume = exynos_pinctrl_resume ,
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+ }, {
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+ /* pin-controller instance 1 PERIC data */
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+ .pin_banks = fsd_pin_banks1 ,
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+ .nr_banks = ARRAY_SIZE (fsd_pin_banks1 ),
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+ .eint_gpio_init = exynos_eint_gpio_init ,
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+ .suspend = exynos_pinctrl_suspend ,
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+ .resume = exynos_pinctrl_resume ,
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+ }, {
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+ /* pin-controller instance 2 PMU data */
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+ .pin_banks = fsd_pin_banks2 ,
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+ .nr_banks = ARRAY_SIZE (fsd_pin_banks2 ),
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+ },
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+ };
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+
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+ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
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+ .ctrl = fsd_pin_ctrl ,
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+ .num_ctrl = ARRAY_SIZE (fsd_pin_ctrl ),
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+ };
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