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pcornuBenjamin-Gaignard
pcornu
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Benjamin-Gaignard
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drm/stm: ltdc: Lindent and minor cleanups
Lindent then checkpatch --strict cleanups Signed-off-by: Philippe CORNU <[email protected]> Reviewed-by: Benjamin Gaignard <[email protected]> Signed-off-by: Benjamin Gaignard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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‎drivers/gpu/drm/stm/ltdc.c

Lines changed: 85 additions & 87 deletions
Original file line numberDiff line numberDiff line change
@@ -42,52 +42,52 @@
4242
* an extra offset specified with reg_ofs.
4343
*/
4444
#define REG_OFS_NONE 0
45-
#define REG_OFS_4 4 /* Insertion of "Layer Configuration 2" reg */
45+
#define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */
4646
#define REG_OFS (ldev->caps.reg_ofs)
47-
#define LAY_OFS 0x80 /* Register Offset between 2 layers */
47+
#define LAY_OFS 0x80 /* Register Offset between 2 layers */
4848

4949
/* Global register offsets */
50-
#define LTDC_IDR 0x0000 /* IDentification */
51-
#define LTDC_LCR 0x0004 /* Layer Count */
52-
#define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */
53-
#define LTDC_BPCR 0x000C /* Back Porch Configuration */
54-
#define LTDC_AWCR 0x0010 /* Active Width Configuration */
55-
#define LTDC_TWCR 0x0014 /* Total Width Configuration */
56-
#define LTDC_GCR 0x0018 /* Global Control */
57-
#define LTDC_GC1R 0x001C /* Global Configuration 1 */
58-
#define LTDC_GC2R 0x0020 /* Global Configuration 2 */
59-
#define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */
60-
#define LTDC_GACR 0x0028 /* GAmma Correction */
61-
#define LTDC_BCCR 0x002C /* Background Color Configuration */
62-
#define LTDC_IER 0x0034 /* Interrupt Enable */
63-
#define LTDC_ISR 0x0038 /* Interrupt Status */
64-
#define LTDC_ICR 0x003C /* Interrupt Clear */
65-
#define LTDC_LIPCR 0x0040 /* Line Interrupt Position Configuration */
66-
#define LTDC_CPSR 0x0044 /* Current Position Status */
67-
#define LTDC_CDSR 0x0048 /* Current Display Status */
50+
#define LTDC_IDR 0x0000 /* IDentification */
51+
#define LTDC_LCR 0x0004 /* Layer Count */
52+
#define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */
53+
#define LTDC_BPCR 0x000C /* Back Porch Configuration */
54+
#define LTDC_AWCR 0x0010 /* Active Width Configuration */
55+
#define LTDC_TWCR 0x0014 /* Total Width Configuration */
56+
#define LTDC_GCR 0x0018 /* Global Control */
57+
#define LTDC_GC1R 0x001C /* Global Configuration 1 */
58+
#define LTDC_GC2R 0x0020 /* Global Configuration 2 */
59+
#define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */
60+
#define LTDC_GACR 0x0028 /* GAmma Correction */
61+
#define LTDC_BCCR 0x002C /* Background Color Configuration */
62+
#define LTDC_IER 0x0034 /* Interrupt Enable */
63+
#define LTDC_ISR 0x0038 /* Interrupt Status */
64+
#define LTDC_ICR 0x003C /* Interrupt Clear */
65+
#define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */
66+
#define LTDC_CPSR 0x0044 /* Current Position Status */
67+
#define LTDC_CDSR 0x0048 /* Current Display Status */
6868

6969
/* Layer register offsets */
70-
#define LTDC_L1LC1R (0x0080) /* L1 Layer Configuration 1 */
71-
#define LTDC_L1LC2R (0x0084) /* L1 Layer Configuration 2 */
72-
#define LTDC_L1CR (0x0084 + REG_OFS) /* L1 Control */
73-
#define LTDC_L1WHPCR (0x0088 + REG_OFS) /* L1 Window Hor Position Config */
74-
#define LTDC_L1WVPCR (0x008C + REG_OFS) /* L1 Window Vert Position Config */
75-
#define LTDC_L1CKCR (0x0090 + REG_OFS) /* L1 Color Keying Configuration */
76-
#define LTDC_L1PFCR (0x0094 + REG_OFS) /* L1 Pixel Format Configuration */
77-
#define LTDC_L1CACR (0x0098 + REG_OFS) /* L1 Constant Alpha Config */
78-
#define LTDC_L1DCCR (0x009C + REG_OFS) /* L1 Default Color Configuration */
79-
#define LTDC_L1BFCR (0x00A0 + REG_OFS) /* L1 Blend Factors Configuration */
80-
#define LTDC_L1FBBCR (0x00A4 + REG_OFS) /* L1 FrameBuffer Bus Control */
81-
#define LTDC_L1AFBCR (0x00A8 + REG_OFS) /* L1 AuxFB Control */
82-
#define LTDC_L1CFBAR (0x00AC + REG_OFS) /* L1 Color FrameBuffer Address */
83-
#define LTDC_L1CFBLR (0x00B0 + REG_OFS) /* L1 Color FrameBuffer Length */
84-
#define LTDC_L1CFBLNR (0x00B4 + REG_OFS) /* L1 Color FrameBuffer Line Nb */
85-
#define LTDC_L1AFBAR (0x00B8 + REG_OFS) /* L1 AuxFB Address */
86-
#define LTDC_L1AFBLR (0x00BC + REG_OFS) /* L1 AuxFB Length */
87-
#define LTDC_L1AFBLNR (0x00C0 + REG_OFS) /* L1 AuxFB Line Number */
88-
#define LTDC_L1CLUTWR (0x00C4 + REG_OFS) /* L1 CLUT Write */
89-
#define LTDC_L1YS1R (0x00E0 + REG_OFS) /* L1 YCbCr Scale 1 */
90-
#define LTDC_L1YS2R (0x00E4 + REG_OFS) /* L1 YCbCr Scale 2 */
70+
#define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */
71+
#define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */
72+
#define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */
73+
#define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */
74+
#define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */
75+
#define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */
76+
#define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */
77+
#define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */
78+
#define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */
79+
#define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */
80+
#define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */
81+
#define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */
82+
#define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */
83+
#define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */
84+
#define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */
85+
#define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */
86+
#define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */
87+
#define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */
88+
#define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */
89+
#define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */
90+
#define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */
9191

9292
/* Bit definitions */
9393
#define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
@@ -172,52 +172,52 @@
172172
#define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
173173
#define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
174174

175-
#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
175+
#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
176176

177-
#define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */
178-
#define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
179-
#define BF1_CA 0x400 /* Constant Alpha */
180-
#define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
181-
#define BF2_1CA 0x005 /* 1 - Constant Alpha */
177+
#define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */
178+
#define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
179+
#define BF1_CA 0x400 /* Constant Alpha */
180+
#define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
181+
#define BF2_1CA 0x005 /* 1 - Constant Alpha */
182182

183-
#define NB_PF 8 /* Max nb of HW pixel format */
183+
#define NB_PF 8 /* Max nb of HW pixel format */
184184

185185
enum ltdc_pix_fmt {
186186
PF_NONE,
187187
/* RGB formats */
188-
PF_ARGB8888, /* ARGB [32 bits] */
189-
PF_RGBA8888, /* RGBA [32 bits] */
190-
PF_RGB888, /* RGB [24 bits] */
191-
PF_RGB565, /* RGB [16 bits] */
192-
PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */
193-
PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
188+
PF_ARGB8888, /* ARGB [32 bits] */
189+
PF_RGBA8888, /* RGBA [32 bits] */
190+
PF_RGB888, /* RGB [24 bits] */
191+
PF_RGB565, /* RGB [16 bits] */
192+
PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */
193+
PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
194194
/* Indexed formats */
195-
PF_L8, /* Indexed 8 bits [8 bits] */
196-
PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */
197-
PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */
195+
PF_L8, /* Indexed 8 bits [8 bits] */
196+
PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */
197+
PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */
198198
};
199199

200200
/* The index gives the encoding of the pixel format for an HW version */
201201
static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = {
202-
PF_ARGB8888, /* 0x00 */
203-
PF_RGB888, /* 0x01 */
204-
PF_RGB565, /* 0x02 */
205-
PF_ARGB1555, /* 0x03 */
206-
PF_ARGB4444, /* 0x04 */
207-
PF_L8, /* 0x05 */
208-
PF_AL44, /* 0x06 */
209-
PF_AL88 /* 0x07 */
202+
PF_ARGB8888, /* 0x00 */
203+
PF_RGB888, /* 0x01 */
204+
PF_RGB565, /* 0x02 */
205+
PF_ARGB1555, /* 0x03 */
206+
PF_ARGB4444, /* 0x04 */
207+
PF_L8, /* 0x05 */
208+
PF_AL44, /* 0x06 */
209+
PF_AL88 /* 0x07 */
210210
};
211211

212212
static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
213-
PF_ARGB8888, /* 0x00 */
214-
PF_RGB888, /* 0x01 */
215-
PF_RGB565, /* 0x02 */
216-
PF_RGBA8888, /* 0x03 */
217-
PF_AL44, /* 0x04 */
218-
PF_L8, /* 0x05 */
219-
PF_ARGB1555, /* 0x06 */
220-
PF_ARGB4444 /* 0x07 */
213+
PF_ARGB8888, /* 0x00 */
214+
PF_RGB888, /* 0x01 */
215+
PF_RGB565, /* 0x02 */
216+
PF_RGBA8888, /* 0x03 */
217+
PF_AL44, /* 0x04 */
218+
PF_L8, /* 0x05 */
219+
PF_ARGB1555, /* 0x06 */
220+
PF_ARGB4444 /* 0x07 */
221221
};
222222

223223
static inline u32 reg_read(void __iomem *base, u32 reg)
@@ -294,7 +294,7 @@ static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
294294
default:
295295
pf = PF_NONE;
296296
break;
297-
/* Note: There are no DRM_FORMAT for AL44 and AL88 */
297+
/* Note: There are no DRM_FORMAT for AL44 and AL88 */
298298
}
299299

300300
return pf;
@@ -317,8 +317,8 @@ static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf)
317317
return DRM_FORMAT_ARGB4444;
318318
case PF_L8:
319319
return DRM_FORMAT_C8;
320-
case PF_AL44: /* No DRM support */
321-
case PF_AL88: /* No DRM support */
320+
case PF_AL44: /* No DRM support */
321+
case PF_AL88: /* No DRM support */
322322
case PF_NONE:
323323
default:
324324
return 0;
@@ -602,11 +602,11 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
602602
src_w = state->src_w >> 16;
603603
src_h = state->src_h >> 16;
604604

605-
DRM_DEBUG_DRIVER(
606-
"plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
607-
plane->base.id, fb->base.id,
608-
src_w, src_h, src_x, src_y,
609-
state->crtc_w, state->crtc_h, state->crtc_x, state->crtc_y);
605+
DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
606+
plane->base.id, fb->base.id,
607+
src_w, src_h, src_x, src_y,
608+
state->crtc_w, state->crtc_h,
609+
state->crtc_x, state->crtc_y);
610610

611611
bpcr = reg_read(ldev->regs, LTDC_BPCR);
612612
ahbp = (bpcr & BPCR_AHBP) >> 16;
@@ -631,7 +631,7 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
631631
if (val == NB_PF) {
632632
DRM_ERROR("Pixel format %.4s not supported\n",
633633
(char *)&fb->format->format);
634-
val = 0; /* set by default ARGB 32 bits */
634+
val = 0; /* set by default ARGB 32 bits */
635635
}
636636
reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
637637

@@ -645,8 +645,7 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
645645

646646
/* Specifies the constant alpha value */
647647
val = CONSTA_MAX;
648-
reg_update_bits(ldev->regs, LTDC_L1CACR + lofs,
649-
LXCACR_CONSTA, val);
648+
reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val);
650649

651650
/* Specifies the blending factors */
652651
val = BF1_PAXCA | BF2_1PAXCA;
@@ -655,8 +654,7 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
655654

656655
/* Configures the frame buffer line number */
657656
val = y1 - y0 + 1;
658-
reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs,
659-
LXCFBLNR_CFBLN, val);
657+
reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val);
660658

661659
/* Sets the FB address */
662660
paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0);
@@ -817,7 +815,7 @@ static int ltdc_encoder_init(struct drm_device *ddev)
817815
return -ENOMEM;
818816

819817
encoder->possible_crtcs = CRTC_MASK;
820-
encoder->possible_clones = 0; /* No cloning support */
818+
encoder->possible_clones = 0; /* No cloning support */
821819

822820
drm_encoder_init(ddev, encoder, &ltdc_encoder_funcs,
823821
DRM_MODE_ENCODER_DPI, NULL);

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