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#include <linux/dmi.h>
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#include "iwl-trans.h"
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#include "iwl-fh.h"
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- #include "iwl-context-info-gen3 .h"
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+ #include "iwl-context-info-v2 .h"
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#include "internal.h"
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#include "iwl-prph.h"
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@@ -97,12 +97,12 @@ iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans,
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* control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags ;
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}
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- int iwl_pcie_ctxt_info_gen3_alloc (struct iwl_trans * trans ,
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- const struct iwl_fw * fw ,
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- const struct fw_img * img )
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+ int iwl_pcie_ctxt_info_v2_alloc (struct iwl_trans * trans ,
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+ const struct iwl_fw * fw ,
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+ const struct fw_img * img )
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{
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struct iwl_trans_pcie * trans_pcie = IWL_TRANS_GET_PCIE_TRANS (trans );
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- struct iwl_context_info_gen3 * ctxt_info_gen3 ;
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+ struct iwl_context_info_v2 * ctxt_info_v2 ;
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struct iwl_prph_scratch * prph_scratch ;
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struct iwl_prph_scratch_ctrl_cfg * prph_sc_ctrl ;
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struct iwl_prph_info * prph_info ;
@@ -213,18 +213,18 @@ int iwl_pcie_ctxt_info_gen3_alloc(struct iwl_trans *trans,
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}
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/* Allocate context info */
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- ctxt_info_gen3 = dma_alloc_coherent (trans -> dev ,
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- sizeof (* ctxt_info_gen3 ),
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- & trans_pcie -> ctxt_info_dma_addr ,
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- GFP_KERNEL );
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- if (!ctxt_info_gen3 ) {
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+ ctxt_info_v2 = dma_alloc_coherent (trans -> dev ,
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+ sizeof (* ctxt_info_v2 ),
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+ & trans_pcie -> ctxt_info_dma_addr ,
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+ GFP_KERNEL );
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+ if (!ctxt_info_v2 ) {
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ret = - ENOMEM ;
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goto err_free_prph_info ;
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}
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- ctxt_info_gen3 -> prph_info_base_addr =
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+ ctxt_info_v2 -> prph_info_base_addr =
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cpu_to_le64 (trans_pcie -> prph_info_dma_addr );
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- ctxt_info_gen3 -> prph_scratch_base_addr =
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+ ctxt_info_v2 -> prph_scratch_base_addr =
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cpu_to_le64 (trans_pcie -> prph_scratch_dma_addr );
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/*
@@ -236,29 +236,29 @@ int iwl_pcie_ctxt_info_gen3_alloc(struct iwl_trans *trans,
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sizeof (prph_scratch -> dram .fseq_img ) !=
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sizeof (* prph_scratch ));
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if (control_flags_ext & IWL_PRPH_SCRATCH_EXT_EXT_FSEQ )
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- ctxt_info_gen3 -> prph_scratch_size =
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+ ctxt_info_v2 -> prph_scratch_size =
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cpu_to_le32 (sizeof (* prph_scratch ));
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else
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- ctxt_info_gen3 -> prph_scratch_size =
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+ ctxt_info_v2 -> prph_scratch_size =
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cpu_to_le32 (offsetofend (typeof (* prph_scratch ),
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dram .common ));
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- ctxt_info_gen3 -> cr_head_idx_arr_base_addr =
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+ ctxt_info_v2 -> cr_head_idx_arr_base_addr =
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cpu_to_le64 (trans_pcie -> rxq -> rb_stts_dma );
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- ctxt_info_gen3 -> tr_tail_idx_arr_base_addr =
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+ ctxt_info_v2 -> tr_tail_idx_arr_base_addr =
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cpu_to_le64 (trans_pcie -> prph_info_dma_addr + PAGE_SIZE / 2 );
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- ctxt_info_gen3 -> cr_tail_idx_arr_base_addr =
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+ ctxt_info_v2 -> cr_tail_idx_arr_base_addr =
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cpu_to_le64 (trans_pcie -> prph_info_dma_addr + 3 * PAGE_SIZE / 4 );
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- ctxt_info_gen3 -> mtr_base_addr =
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+ ctxt_info_v2 -> mtr_base_addr =
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cpu_to_le64 (trans_pcie -> txqs .txq [trans -> conf .cmd_queue ]-> dma_addr );
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- ctxt_info_gen3 -> mcr_base_addr =
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+ ctxt_info_v2 -> mcr_base_addr =
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cpu_to_le64 (trans_pcie -> rxq -> used_bd_dma );
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- ctxt_info_gen3 -> mtr_size =
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+ ctxt_info_v2 -> mtr_size =
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cpu_to_le16 (TFD_QUEUE_CB_SIZE (cmdq_size ));
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- ctxt_info_gen3 -> mcr_size =
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+ ctxt_info_v2 -> mcr_size =
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cpu_to_le16 (RX_QUEUE_CB_SIZE (iwl_trans_get_num_rbds (trans )));
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- trans_pcie -> ctxt_info_gen3 = ctxt_info_gen3 ;
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+ trans_pcie -> ctxt_info_v2 = ctxt_info_v2 ;
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trans_pcie -> prph_info = prph_info ;
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trans_pcie -> prph_scratch = prph_scratch ;
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@@ -277,10 +277,10 @@ int iwl_pcie_ctxt_info_gen3_alloc(struct iwl_trans *trans,
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return 0 ;
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err_free_ctxt_info :
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- dma_free_coherent (trans -> dev , sizeof (* trans_pcie -> ctxt_info_gen3 ),
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- trans_pcie -> ctxt_info_gen3 ,
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+ dma_free_coherent (trans -> dev , sizeof (* trans_pcie -> ctxt_info_v2 ),
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+ trans_pcie -> ctxt_info_v2 ,
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trans_pcie -> ctxt_info_dma_addr );
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- trans_pcie -> ctxt_info_gen3 = NULL ;
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+ trans_pcie -> ctxt_info_v2 = NULL ;
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err_free_prph_info :
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dma_free_coherent (trans -> dev , PAGE_SIZE , prph_info ,
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trans_pcie -> prph_info_dma_addr );
@@ -294,7 +294,7 @@ int iwl_pcie_ctxt_info_gen3_alloc(struct iwl_trans *trans,
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}
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- void iwl_pcie_ctxt_info_gen3_kick (struct iwl_trans * trans )
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+ void iwl_pcie_ctxt_info_v2_kick (struct iwl_trans * trans )
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{
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struct iwl_trans_pcie * trans_pcie = IWL_TRANS_GET_PCIE_TRANS (trans );
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@@ -309,7 +309,7 @@ void iwl_pcie_ctxt_info_gen3_kick(struct iwl_trans *trans)
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CSR_AUTO_FUNC_BOOT_ENA );
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}
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- void iwl_pcie_ctxt_info_gen3_free (struct iwl_trans * trans , bool alive )
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+ void iwl_pcie_ctxt_info_v2_free (struct iwl_trans * trans , bool alive )
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{
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struct iwl_trans_pcie * trans_pcie = IWL_TRANS_GET_PCIE_TRANS (trans );
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@@ -327,15 +327,15 @@ void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive)
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if (alive )
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return ;
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- if (!trans_pcie -> ctxt_info_gen3 )
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+ if (!trans_pcie -> ctxt_info_v2 )
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return ;
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- /* ctxt_info_gen3 and prph_scratch are still needed for PNVM load */
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- dma_free_coherent (trans -> dev , sizeof (* trans_pcie -> ctxt_info_gen3 ),
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- trans_pcie -> ctxt_info_gen3 ,
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+ /* ctxt_info_v2 and prph_scratch are still needed for PNVM load */
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+ dma_free_coherent (trans -> dev , sizeof (* trans_pcie -> ctxt_info_v2 ),
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+ trans_pcie -> ctxt_info_v2 ,
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trans_pcie -> ctxt_info_dma_addr );
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trans_pcie -> ctxt_info_dma_addr = 0 ;
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- trans_pcie -> ctxt_info_gen3 = NULL ;
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+ trans_pcie -> ctxt_info_v2 = NULL ;
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dma_free_coherent (trans -> dev , sizeof (* trans_pcie -> prph_scratch ),
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trans_pcie -> prph_scratch ,
@@ -439,9 +439,9 @@ static int iwl_pcie_load_payloads_segments
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}
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- int iwl_trans_pcie_ctx_info_gen3_load_pnvm (struct iwl_trans * trans ,
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- const struct iwl_pnvm_image * pnvm_payloads ,
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- const struct iwl_ucode_capabilities * capa )
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+ int iwl_trans_pcie_ctx_info_v2_load_pnvm (struct iwl_trans * trans ,
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+ const struct iwl_pnvm_image * pnvm_payloads ,
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+ const struct iwl_ucode_capabilities * capa )
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{
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struct iwl_trans_pcie * trans_pcie = IWL_TRANS_GET_PCIE_TRANS (trans );
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struct iwl_prph_scratch_ctrl_cfg * prph_sc_ctrl =
@@ -521,8 +521,8 @@ static void iwl_pcie_set_contig_pnvm(struct iwl_trans *trans)
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cpu_to_le32 (trans_pcie -> pnvm_data .drams [0 ].size );
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}
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- void iwl_trans_pcie_ctx_info_gen3_set_pnvm (struct iwl_trans * trans ,
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- const struct iwl_ucode_capabilities * capa )
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+ void iwl_trans_pcie_ctx_info_v2_set_pnvm (struct iwl_trans * trans ,
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+ const struct iwl_ucode_capabilities * capa )
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{
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if (trans -> mac_cfg -> device_family < IWL_DEVICE_FAMILY_AX210 )
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return ;
@@ -533,9 +533,9 @@ void iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
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iwl_pcie_set_contig_pnvm (trans );
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}
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- int iwl_trans_pcie_ctx_info_gen3_load_reduce_power (struct iwl_trans * trans ,
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- const struct iwl_pnvm_image * payloads ,
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- const struct iwl_ucode_capabilities * capa )
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+ int iwl_trans_pcie_ctx_info_v2_load_reduce_power (struct iwl_trans * trans ,
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+ const struct iwl_pnvm_image * payloads ,
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+ const struct iwl_ucode_capabilities * capa )
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{
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struct iwl_trans_pcie * trans_pcie = IWL_TRANS_GET_PCIE_TRANS (trans );
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struct iwl_prph_scratch_ctrl_cfg * prph_sc_ctrl =
@@ -604,8 +604,8 @@ static void iwl_pcie_set_contig_reduce_power(struct iwl_trans *trans)
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}
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void
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- iwl_trans_pcie_ctx_info_gen3_set_reduce_power (struct iwl_trans * trans ,
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- const struct iwl_ucode_capabilities * capa )
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+ iwl_trans_pcie_ctx_info_v2_set_reduce_power (struct iwl_trans * trans ,
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+ const struct iwl_ucode_capabilities * capa )
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{
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if (trans -> mac_cfg -> device_family < IWL_DEVICE_FAMILY_AX210 )
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return ;
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