@@ -1309,48 +1309,6 @@ void b53_port_event(struct dsa_switch *ds, int port)
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}
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EXPORT_SYMBOL (b53_port_event );
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- void b53_phylink_validate (struct dsa_switch * ds , int port ,
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- unsigned long * supported ,
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- struct phylink_link_state * state )
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- {
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- struct b53_device * dev = ds -> priv ;
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- __ETHTOOL_DECLARE_LINK_MODE_MASK (mask ) = { 0 , };
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-
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- if (dev -> ops -> serdes_phylink_validate )
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- dev -> ops -> serdes_phylink_validate (dev , port , mask , state );
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-
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- /* Allow all the expected bits */
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- phylink_set (mask , Autoneg );
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- phylink_set_port_modes (mask );
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- phylink_set (mask , Pause );
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- phylink_set (mask , Asym_Pause );
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-
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- /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we
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- * support Gigabit, including Half duplex.
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- *
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- * FIXME: this is weird - 802.3z is always Gigabit, but we exclude
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- * it here. Why? This makes no sense.
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- */
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- if (!(state -> interface == PHY_INTERFACE_MODE_MII ||
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- state -> interface == PHY_INTERFACE_MODE_REVMII ||
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- phy_interface_mode_is_8023z (state -> interface ) ||
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- is5325 (dev ) || is5365 (dev ))) {
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- phylink_set (mask , 1000b aseT_Full );
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- phylink_set (mask , 1000b aseT_Half );
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- }
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-
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- if (!phy_interface_mode_is_8023z (state -> interface )) {
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- phylink_set (mask , 10b aseT_Half );
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- phylink_set (mask , 10b aseT_Full );
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- phylink_set (mask , 100b aseT_Half );
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- phylink_set (mask , 100b aseT_Full );
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- }
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-
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- linkmode_and (supported , supported , mask );
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- linkmode_and (state -> advertising , state -> advertising , mask );
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- }
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- EXPORT_SYMBOL (b53_phylink_validate );
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-
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static void b53_phylink_get_caps (struct dsa_switch * ds , int port ,
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struct phylink_config * config )
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{
@@ -1362,14 +1320,26 @@ static void b53_phylink_get_caps(struct dsa_switch *ds, int port,
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/* These switches appear to support MII and RevMII too, but beyond
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* this, the code gives very few clues. FIXME: We probably need more
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* interface modes here.
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+ *
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+ * According to b53_srab_mux_init(), ports 3..5 can support:
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+ * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting.
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+ * However, the interface mode read from the MUX configuration is
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+ * not passed back to DSA, so phylink uses NA.
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+ * DT can specify RGMII for ports 0, 1.
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+ * For MDIO, port 8 can be RGMII_TXID.
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*/
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__set_bit (PHY_INTERFACE_MODE_MII , config -> supported_interfaces );
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__set_bit (PHY_INTERFACE_MODE_REVMII , config -> supported_interfaces );
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config -> mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
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MAC_10 | MAC_100 ;
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- /* 5325/5365 are not capable of gigabit speeds, everything else is */
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+ /* 5325/5365 are not capable of gigabit speeds, everything else is.
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+ * Note: the original code also exclulded Gigagbit for MII, RevMII
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+ * and 802.3z modes. MII and RevMII are not able to work above 100M,
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+ * so will be excluded by the generic validator implementation.
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+ * However, the exclusion of Gigabit for 802.3z just seems wrong.
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+ */
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if (!(is5325 (dev ) || is5365 (dev )))
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config -> mac_capabilities |= MAC_1000 ;
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@@ -2288,7 +2258,6 @@ static const struct dsa_switch_ops b53_switch_ops = {
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.phy_write = b53_phy_write16 ,
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.adjust_link = b53_adjust_link ,
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.phylink_get_caps = b53_phylink_get_caps ,
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- .phylink_validate = b53_phylink_validate ,
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.phylink_mac_link_state = b53_phylink_mac_link_state ,
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.phylink_mac_config = b53_phylink_mac_config ,
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.phylink_mac_an_restart = b53_phylink_mac_an_restart ,
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