@@ -120,11 +120,23 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
120
120
ih_rb_cntl = REG_SET_FIELD (ih_rb_cntl , IH_RB_CNTL_RING1 ,
121
121
RB_USED_INT_THRESHOLD , threshold );
122
122
123
- WREG32_SOC15 (OSSSYS , 0 , mmIH_RB_CNTL_RING1 , ih_rb_cntl );
123
+ if (amdgpu_sriov_vf (adev ) && amdgpu_sriov_reg_indirect_ih (adev )) {
124
+ if (psp_reg_program (& adev -> psp , PSP_REG_IH_RB_CNTL_RING1 , ih_rb_cntl ))
125
+ return ;
126
+ } else {
127
+ WREG32_SOC15 (OSSSYS , 0 , mmIH_RB_CNTL_RING1 , ih_rb_cntl );
128
+ }
129
+
124
130
ih_rb_cntl = RREG32_SOC15 (OSSSYS , 0 , mmIH_RB_CNTL_RING2 );
125
131
ih_rb_cntl = REG_SET_FIELD (ih_rb_cntl , IH_RB_CNTL_RING2 ,
126
132
RB_USED_INT_THRESHOLD , threshold );
127
- WREG32_SOC15 (OSSSYS , 0 , mmIH_RB_CNTL_RING2 , ih_rb_cntl );
133
+ if (amdgpu_sriov_vf (adev ) && amdgpu_sriov_reg_indirect_ih (adev )) {
134
+ if (psp_reg_program (& adev -> psp , PSP_REG_IH_RB_CNTL_RING2 , ih_rb_cntl ))
135
+ return ;
136
+ } else {
137
+ WREG32_SOC15 (OSSSYS , 0 , mmIH_RB_CNTL_RING2 , ih_rb_cntl );
138
+ }
139
+
128
140
WREG32_SOC15 (OSSSYS , 0 , mmIH_CNTL2 , ih_cntl );
129
141
}
130
142
@@ -153,10 +165,8 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
153
165
tmp = REG_SET_FIELD (tmp , IH_RB_CNTL , ENABLE_INTR , (enable ? 1 : 0 ));
154
166
155
167
if (amdgpu_sriov_vf (adev ) && amdgpu_sriov_reg_indirect_ih (adev )) {
156
- if (psp_reg_program (& adev -> psp , ih_regs -> psp_reg_id , tmp )) {
157
- DRM_ERROR ("PSP program IH_RB_CNTL failed!\n" );
168
+ if (psp_reg_program (& adev -> psp , ih_regs -> psp_reg_id , tmp ))
158
169
return - ETIMEDOUT ;
159
- }
160
170
} else {
161
171
WREG32 (ih_regs -> ih_rb_cntl , tmp );
162
172
}
0 commit comments