@@ -585,71 +585,6 @@ enum RPADIR_BIT {
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/* FDR */
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#define DEFAULT_FDR_INIT 0x00000707
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- enum phy_offsets {
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- PHY_CTRL = 0 , PHY_STAT = 1 , PHY_IDT1 = 2 , PHY_IDT2 = 3 ,
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- PHY_ANA = 4 , PHY_ANL = 5 , PHY_ANE = 6 ,
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- PHY_16 = 16 ,
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- };
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-
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- /* PHY_CTRL */
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- enum PHY_CTRL_BIT {
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- PHY_C_RESET = 0x8000 , PHY_C_LOOPBK = 0x4000 , PHY_C_SPEEDSL = 0x2000 ,
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- PHY_C_ANEGEN = 0x1000 , PHY_C_PWRDN = 0x0800 , PHY_C_ISO = 0x0400 ,
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- PHY_C_RANEG = 0x0200 , PHY_C_DUPLEX = 0x0100 , PHY_C_COLT = 0x0080 ,
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- };
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- #define DM9161_PHY_C_ANEGEN 0 /* auto nego special */
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-
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- /* PHY_STAT */
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- enum PHY_STAT_BIT {
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- PHY_S_100T4 = 0x8000 , PHY_S_100X_F = 0x4000 , PHY_S_100X_H = 0x2000 ,
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- PHY_S_10T_F = 0x1000 , PHY_S_10T_H = 0x0800 , PHY_S_ANEGC = 0x0020 ,
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- PHY_S_RFAULT = 0x0010 , PHY_S_ANEGA = 0x0008 , PHY_S_LINK = 0x0004 ,
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- PHY_S_JAB = 0x0002 , PHY_S_EXTD = 0x0001 ,
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- };
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-
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- /* PHY_ANA */
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- enum PHY_ANA_BIT {
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- PHY_A_NP = 0x8000 , PHY_A_ACK = 0x4000 , PHY_A_RF = 0x2000 ,
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- PHY_A_FCS = 0x0400 , PHY_A_T4 = 0x0200 , PHY_A_FDX = 0x0100 ,
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- PHY_A_HDX = 0x0080 , PHY_A_10FDX = 0x0040 , PHY_A_10HDX = 0x0020 ,
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- PHY_A_SEL = 0x001e ,
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- };
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- /* PHY_ANL */
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- enum PHY_ANL_BIT {
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- PHY_L_NP = 0x8000 , PHY_L_ACK = 0x4000 , PHY_L_RF = 0x2000 ,
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- PHY_L_FCS = 0x0400 , PHY_L_T4 = 0x0200 , PHY_L_FDX = 0x0100 ,
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- PHY_L_HDX = 0x0080 , PHY_L_10FDX = 0x0040 , PHY_L_10HDX = 0x0020 ,
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- PHY_L_SEL = 0x001f ,
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- };
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-
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- /* PHY_ANE */
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- enum PHY_ANE_BIT {
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- PHY_E_PDF = 0x0010 , PHY_E_LPNPA = 0x0008 , PHY_E_NPA = 0x0004 ,
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- PHY_E_PRX = 0x0002 , PHY_E_LPANEGA = 0x0001 ,
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- };
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-
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- /* DM9161 */
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- enum PHY_16_BIT {
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- PHY_16_BP4B45 = 0x8000 , PHY_16_BPSCR = 0x4000 , PHY_16_BPALIGN = 0x2000 ,
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- PHY_16_BP_ADPOK = 0x1000 , PHY_16_Repeatmode = 0x0800 ,
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- PHY_16_TXselect = 0x0400 ,
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- PHY_16_Rsvd = 0x0200 , PHY_16_RMIIEnable = 0x0100 ,
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- PHY_16_Force100LNK = 0x0080 ,
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- PHY_16_APDLED_CTL = 0x0040 , PHY_16_COLLED_CTL = 0x0020 ,
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- PHY_16_RPDCTR_EN = 0x0010 ,
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- PHY_16_ResetStMch = 0x0008 , PHY_16_PreamSupr = 0x0004 ,
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- PHY_16_Sleepmode = 0x0002 ,
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- PHY_16_RemoteLoopOut = 0x0001 ,
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- };
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-
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- #define POST_RX 0x08
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- #define POST_FW 0x04
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- #define POST0_RX (POST_RX)
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- #define POST0_FW (POST_FW)
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- #define POST1_RX (POST_RX >> 2)
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- #define POST1_FW (POST_FW >> 2)
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- #define POST_ALL (POST0_RX | POST0_FW | POST1_RX | POST1_FW)
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-
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/* ARSTR */
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enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001 , };
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@@ -786,10 +721,6 @@ struct sh_eth_private {
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int msg_enable ;
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int speed ;
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int duplex ;
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- u32 rx_int_var , tx_int_var ; /* interrupt control variables */
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- char post_rx ; /* POST receive */
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- char post_fw ; /* POST forward */
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- struct net_device_stats tsu_stats ; /* TSU forward status */
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int port ; /* for TSU */
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int vlan_num_ids ; /* for VLAN tag filter */
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