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clk: starfive: Add JH7100 audio clock driver
Add a driver for the audio clocks on the Starfive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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‎MAINTAINERS

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@@ -18376,12 +18376,12 @@ M: Ion Badulescu <[email protected]>
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S: Odd Fixes
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F: drivers/net/ethernet/adaptec/starfire*
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STARFIVE JH7100 CLOCK DRIVER
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STARFIVE JH7100 CLOCK DRIVERS
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M: Emil Renner Berthing <[email protected]>
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S: Maintained
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F: Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
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F: drivers/clk/starfive/clk-starfive-jh7100.c
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F: include/dt-bindings/clock/starfive-jh7100.h
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F: Documentation/devicetree/bindings/clock/starfive,jh7100-*.yaml
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F: drivers/clk/starfive/clk-starfive-jh7100*
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F: include/dt-bindings/clock/starfive-jh7100*.h
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STARFIVE JH7100 PINCTRL DRIVER
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M: Emil Renner Berthing <[email protected]>

‎drivers/clk/starfive/Kconfig

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@@ -7,3 +7,11 @@ config CLK_STARFIVE_JH7100
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help
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Say yes here to support the clock controller on the StarFive JH7100
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SoC.
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config CLK_STARFIVE_JH7100_AUDIO
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tristate "StarFive JH7100 audio clock support"
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depends on CLK_STARFIVE_JH7100
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default m if SOC_STARFIVE
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help
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Say Y or M here to support the audio clocks on the StarFive JH7100
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SoC.

‎drivers/clk/starfive/Makefile

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# SPDX-License-Identifier: GPL-2.0
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# StarFive Clock
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obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
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obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o

‎drivers/clk/starfive/clk-starfive-jh7100-audio.c

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// SPDX-License-Identifier: GPL-2.0
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/*
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* StarFive JH7100 Audio Clock Driver
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*
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* Copyright (C) 2021 Emil Renner Berthing <[email protected]>
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*/
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#include <linux/bits.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/starfive-jh7100-audio.h>
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#include "clk-starfive-jh7100.h"
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/* external clocks */
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#define JH7100_AUDCLK_AUDIO_SRC (JH7100_AUDCLK_END + 0)
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#define JH7100_AUDCLK_AUDIO_12288 (JH7100_AUDCLK_END + 1)
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#define JH7100_AUDCLK_DOM7AHB_BUS (JH7100_AUDCLK_END + 2)
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#define JH7100_AUDCLK_I2SADC_BCLK_IOPAD (JH7100_AUDCLK_END + 3)
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#define JH7100_AUDCLK_I2SADC_LRCLK_IOPAD (JH7100_AUDCLK_END + 4)
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#define JH7100_AUDCLK_I2SDAC_BCLK_IOPAD (JH7100_AUDCLK_END + 5)
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#define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD (JH7100_AUDCLK_END + 6)
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#define JH7100_AUDCLK_VAD_INTMEM (JH7100_AUDCLK_END + 7)
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static const struct jh7100_clk_data jh7100_audclk_data[] = {
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JH7100__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
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JH7100_AUDCLK_AUDIO_SRC,
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JH7100_AUDCLK_AUDIO_12288),
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JH7100__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
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JH7100_AUDCLK_AUDIO_SRC,
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JH7100_AUDCLK_AUDIO_12288),
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JH7100_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
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JH7100_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
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JH7100_AUDCLK_ADC_MCLK,
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JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
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JH7100__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
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JH7100_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
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JH7100_AUDCLK_I2SADC_BCLK_N,
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JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
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JH7100_AUDCLK_I2SADC_BCLK),
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JH7100_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
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JH7100__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
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JH7100_AUDCLK_AUDIO_SRC,
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JH7100_AUDCLK_AUDIO_12288),
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JH7100_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
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JH7100__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
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JH7100_AUDCLK_AUDIO_SRC,
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JH7100_AUDCLK_AUDIO_12288),
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JH7100_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
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JH7100_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
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JH7100__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
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JH7100_AUDCLK_AUDIO_SRC,
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JH7100_AUDCLK_AUDIO_12288),
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JH7100_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
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JH7100_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
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JH7100_AUDCLK_DAC_MCLK,
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JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
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JH7100__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
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JH7100_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
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JH7100_AUDCLK_I2S1_MCLK,
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JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
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JH7100_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
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JH7100_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
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JH7100_AUDCLK_I2S1_MCLK,
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JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
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JH7100__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
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JH7100_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
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JH7100_AUDCLK_I2S1_BCLK_N,
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JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
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JH7100_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
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JH7100__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
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JH7100_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
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JH7100_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
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JH7100_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
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JH7100_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
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JH7100__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
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JH7100__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
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JH7100_AUDCLK_VAD_INTMEM,
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JH7100_AUDCLK_AUDIO_12288),
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};
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static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data)
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{
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struct jh7100_clk_priv *priv = data;
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unsigned int idx = clkspec->args[0];
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if (idx < JH7100_AUDCLK_END)
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return &priv->reg[idx].hw;
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return ERR_PTR(-EINVAL);
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}
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static int jh7100_audclk_probe(struct platform_device *pdev)
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{
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struct jh7100_clk_priv *priv;
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unsigned int idx;
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int ret;
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priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_AUDCLK_END), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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spin_lock_init(&priv->rmw_lock);
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priv->dev = &pdev->dev;
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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for (idx = 0; idx < JH7100_AUDCLK_END; idx++) {
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u32 max = jh7100_audclk_data[idx].max;
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struct clk_parent_data parents[4] = {};
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struct clk_init_data init = {
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.name = jh7100_audclk_data[idx].name,
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.ops = starfive_jh7100_clk_ops(max),
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.parent_data = parents,
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.num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
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.flags = jh7100_audclk_data[idx].flags,
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};
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struct jh7100_clk *clk = &priv->reg[idx];
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unsigned int i;
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for (i = 0; i < init.num_parents; i++) {
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unsigned int pidx = jh7100_audclk_data[idx].parents[i];
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if (pidx < JH7100_AUDCLK_END)
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parents[i].hw = &priv->reg[pidx].hw;
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else if (pidx == JH7100_AUDCLK_AUDIO_SRC)
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parents[i].fw_name = "audio_src";
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else if (pidx == JH7100_AUDCLK_AUDIO_12288)
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parents[i].fw_name = "audio_12288";
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else if (pidx == JH7100_AUDCLK_DOM7AHB_BUS)
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parents[i].fw_name = "dom7ahb_bus";
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}
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clk->hw.init = &init;
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clk->idx = idx;
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clk->max_div = max & JH7100_CLK_DIV_MASK;
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ret = devm_clk_hw_register(priv->dev, &clk->hw);
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if (ret)
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return ret;
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}
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return devm_of_clk_add_hw_provider(priv->dev, jh7100_audclk_get, priv);
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}
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static const struct of_device_id jh7100_audclk_match[] = {
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{ .compatible = "starfive,jh7100-audclk" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, jh7100_audclk_match);
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static struct platform_driver jh7100_audclk_driver = {
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.probe = jh7100_audclk_probe,
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.driver = {
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.name = "clk-starfive-jh7100-audio",
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.of_match_table = jh7100_audclk_match,
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},
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};
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module_platform_driver(jh7100_audclk_driver);
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MODULE_AUTHOR("Emil Renner Berthing");
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MODULE_DESCRIPTION("StarFive JH7100 audio clock driver");
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MODULE_LICENSE("GPL v2");

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