@@ -206,9 +206,9 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev,
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/* update the scanout addresses */
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WREG32 (mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc -> crtc_offset ,
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upper_32_bits (crtc_base ));
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+ /* writing to the low address triggers the update */
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WREG32 (mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc -> crtc_offset ,
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(u32 )crtc_base );
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-
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/* post the write */
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RREG32 (mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc -> crtc_offset );
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}
@@ -218,11 +218,11 @@ static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
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{
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if ((crtc < 0 ) || (crtc >= adev -> mode_info .num_crtc ))
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return - EINVAL ;
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+
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* vbl = RREG32 (mmCRTC_V_BLANK_START_END + crtc_offsets [crtc ]);
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* position = RREG32 (mmCRTC_STATUS_POSITION + crtc_offsets [crtc ]);
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return 0 ;
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-
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}
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/**
@@ -1006,6 +1006,18 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
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}
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/* watermark setup */
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+ /**
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+ * dce_v6_0_line_buffer_adjust - Set up the line buffer
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+ *
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+ * @adev: amdgpu_device pointer
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+ * @amdgpu_crtc: the selected display controller
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+ * @mode: the current display mode on the selected display
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+ * controller
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+ *
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+ * Setup up the line buffer allocation for
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+ * the selected display controller (CIK).
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+ * Returns the line buffer size in pixels.
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+ */
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static u32 dce_v6_0_line_buffer_adjust (struct amdgpu_device * adev ,
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struct amdgpu_crtc * amdgpu_crtc ,
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struct drm_display_mode * mode ,
@@ -1386,6 +1398,8 @@ static int dce_v6_0_audio_init(struct amdgpu_device *adev)
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adev -> mode_info .audio .pin [i ].connected = false;
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adev -> mode_info .audio .pin [i ].offset = pin_offsets [i ];
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adev -> mode_info .audio .pin [i ].id = i ;
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+ /* disable audio. it will be set up later */
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+ /* XXX remove once we switch to ip funcs */
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dce_v6_0_audio_enable (adev , & adev -> mode_info .audio .pin [i ], false);
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}
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