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Merge tag 'devicetree-fixes-for-5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree fixes from Rob Herring: - Clean-up missing '/schemas' in $ref paths - Fix MediaTek Vcodec decoder example 'dma-ranges' errors - Expand available values of PBL for snps,dwmac to fix warnings in mediatek-dwmac.yaml example - Fix warnings in MediaTek display bindings * tag 'devicetree-fixes-for-5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: dt-bindings: Fix missing '/schemas' in $ref paths dt-bindings: media: mediatek,vcodec: Fix addressing cell sizes dt-bindings: net: snps,dwmac: modify available values of PBL dt-bindings: display: mediatek: Fix examples on new bindings dt-bindings: display: mediatek, ovl: Fix 'iommu' required property typo dt-bindings: display: mediatek, mutex: Fix mediatek, gce-events type Revert "dt-bindings: display: mediatek: add ethdr definition for mt8195"
2 parents 9ae2a14 + 22a41e9 commit 5efabda

28 files changed

+338
-353
lines changed

‎Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml

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@@ -42,7 +42,7 @@ patternProperties:
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description:
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The individual power management domains within this controller
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type: object
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$ref: /power/apple,pmgr-pwrstate.yaml#
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$ref: /schemas/power/apple,pmgr-pwrstate.yaml#
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required:
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- compatible

‎Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml

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@@ -66,12 +66,21 @@ additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/power/mt8173-power.h>
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#include <dt-bindings/gce/mt8173-gce.h>
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70-
aal@14015000 {
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compatible = "mediatek,mt8173-disp-aal";
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reg = <0 0x14015000 0 0x1000>;
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interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_AAL>;
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mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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aal@14015000 {
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compatible = "mediatek,mt8173-disp-aal";
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reg = <0 0x14015000 0 0x1000>;
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interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_AAL>;
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mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
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};
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};

‎Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml

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@@ -65,12 +65,21 @@ additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt8183-clk.h>
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#include <dt-bindings/power/mt8183-power.h>
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#include <dt-bindings/gce/mt8183-gce.h>
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ccorr0: ccorr@1400f000 {
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compatible = "mediatek,mt8183-disp-ccorr";
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reg = <0 0x1400f000 0 0x1000>;
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interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
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clocks = <&mmsys CLK_MM_DISP_CCORR0>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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ccorr0: ccorr@1400f000 {
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compatible = "mediatek,mt8183-disp-ccorr";
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reg = <0 0x1400f000 0 0x1000>;
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interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
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clocks = <&mmsys CLK_MM_DISP_CCORR0>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
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};
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};

‎Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml

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@@ -75,12 +75,21 @@ additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/power/mt8173-power.h>
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#include <dt-bindings/gce/mt8173-gce.h>
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color0: color@14013000 {
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compatible = "mediatek,mt8173-disp-color";
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reg = <0 0x14013000 0 0x1000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_COLOR0>;
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mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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color0: color@14013000 {
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compatible = "mediatek,mt8173-disp-color";
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reg = <0 0x14013000 0 0x1000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_COLOR0>;
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mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
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};
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};

‎Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml

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@@ -65,12 +65,21 @@ additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt8183-clk.h>
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#include <dt-bindings/power/mt8183-power.h>
71+
#include <dt-bindings/gce/mt8183-gce.h>
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dither0: dither@14012000 {
70-
compatible = "mediatek,mt8183-disp-dither";
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reg = <0 0x14012000 0 0x1000>;
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interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
74-
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
75-
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
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soc {
74+
#address-cells = <2>;
75+
#size-cells = <2>;
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77+
dither0: dither@14012000 {
78+
compatible = "mediatek,mt8183-disp-dither";
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reg = <0 0x14012000 0 0x1000>;
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interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
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clocks = <&mmsys CLK_MM_DISP_DITHER0>;
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mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
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};
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};

‎Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml

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@@ -70,8 +70,7 @@ examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt8173-clk.h>
73-
#include <dt-bindings/interrupt-controller/arm-gic.h>
74-
#include <dt-bindings/interrupt-controller/irq.h>
73+
7574
dpi0: dpi@1401d000 {
7675
compatible = "mediatek,mt8173-dpi";
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reg = <0x1401d000 0x1000>;

‎Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml

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@@ -60,12 +60,21 @@ additionalProperties: false
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examples:
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- |
63+
#include <dt-bindings/interrupt-controller/arm-gic.h>
64+
#include <dt-bindings/clock/mt8195-clk.h>
65+
#include <dt-bindings/power/mt8195-power.h>
66+
#include <dt-bindings/gce/mt8195-gce.h>
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dsc0: disp_dsc_wrap@1c009000 {
65-
compatible = "mediatek,mt8195-disp-dsc";
66-
reg = <0 0x1c009000 0 0x1000>;
67-
interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
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clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
70-
mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
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soc {
69+
#address-cells = <2>;
70+
#size-cells = <2>;
71+
72+
dsc0: disp_dsc_wrap@1c009000 {
73+
compatible = "mediatek,mt8195-disp-dsc";
74+
reg = <0 0x1c009000 0 0x1000>;
75+
interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
76+
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
77+
clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
78+
mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
79+
};
7180
};

‎Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml

Lines changed: 0 additions & 147 deletions
This file was deleted.

‎Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml

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@@ -66,12 +66,21 @@ additionalProperties: false
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examples:
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- |
69+
#include <dt-bindings/interrupt-controller/arm-gic.h>
70+
#include <dt-bindings/clock/mt8173-clk.h>
71+
#include <dt-bindings/power/mt8173-power.h>
72+
#include <dt-bindings/gce/mt8173-gce.h>
6973
70-
gamma@14016000 {
71-
compatible = "mediatek,mt8173-disp-gamma";
72-
reg = <0 0x14016000 0 0x1000>;
73-
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
74-
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
75-
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
76-
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
74+
soc {
75+
#address-cells = <2>;
76+
#size-cells = <2>;
77+
78+
gamma@14016000 {
79+
compatible = "mediatek,mt8173-disp-gamma";
80+
reg = <0 0x14016000 0 0x1000>;
81+
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
82+
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
83+
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
84+
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
85+
};
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};

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