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Merge tag 'v6.6-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto updates from Herbert Xu: "API: - Move crypto engine callback from tfm ctx into algorithm object - Fix atomic sleep bug in crypto_destroy_instance - Move lib/mpi into lib/crypto Algorithms: - Add chacha20 and poly1305 implementation for powerpc p10 Drivers: - Add AES skcipher and aead support to starfive - Add Dynamic Boost Control support to ccp - Add support for STM32P13 platform to stm32" * tag 'v6.6-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (149 commits) Revert "dt-bindings: crypto: qcom,prng: Add SM8450" crypto: chelsio - Remove unused declarations X.509: if signature is unsupported skip validation crypto: qat - fix crypto capability detection for 4xxx crypto: drivers - Explicitly include correct DT includes crypto: engine - Remove crypto_engine_ctx crypto: zynqmp - Use new crypto_engine_op interface crypto: virtio - Use new crypto_engine_op interface crypto: stm32 - Use new crypto_engine_op interface crypto: jh7110 - Use new crypto_engine_op interface crypto: rk3288 - Use new crypto_engine_op interface crypto: omap - Use new crypto_engine_op interface crypto: keembay - Use new crypto_engine_op interface crypto: sl3516 - Use new crypto_engine_op interface crypto: caam - Use new crypto_engine_op interface crypto: aspeed - Remove non-standard sha512 algorithms crypto: aspeed - Use new crypto_engine_op interface crypto: amlogic - Use new crypto_engine_op interface crypto: sun8i-ss - Use new crypto_engine_op interface crypto: sun8i-ce - Use new crypto_engine_op interface ...
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‎Documentation/ABI/testing/debugfs-driver-qat

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1+
What: /sys/kernel/debug/qat_<device>_<BDF>/qat/fw_counters
2+
Date: November 2023
3+
KernelVersion: 6.6
4+
Contact: [email protected]
5+
Description: (RO) Read returns the number of requests sent to the FW and the number of responses
6+
received from the FW for each Acceleration Engine
7+
Reported firmware counters::
8+
9+
<N>: Number of requests sent from Acceleration Engine N to FW and responses
10+
Acceleration Engine N received from FW
11+
12+
What: /sys/kernel/debug/qat_<device>_<BDF>/heartbeat/config
13+
Date: November 2023
14+
KernelVersion: 6.6
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Contact: [email protected]
16+
Description: (RW) Read returns value of the Heartbeat update period.
17+
Write to the file changes this period value.
18+
19+
This period should reflect planned polling interval of device
20+
health status. High frequency Heartbeat monitoring wastes CPU cycles
21+
but minimizes the customer’s system downtime. Also, if there are
22+
large service requests that take some time to complete, high frequency
23+
Heartbeat monitoring could result in false reports of unresponsiveness
24+
and in those cases, period needs to be increased.
25+
26+
This parameter is effective only for c3xxx, c62x, dh895xcc devices.
27+
4xxx has this value internally fixed to 200ms.
28+
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Default value is set to 500. Minimal allowed value is 200.
30+
All values are expressed in milliseconds.
31+
32+
What: /sys/kernel/debug/qat_<device>_<BDF>/heartbeat/queries_failed
33+
Date: November 2023
34+
KernelVersion: 6.6
35+
Contact: [email protected]
36+
Description: (RO) Read returns the number of times the device became unresponsive.
37+
38+
Attribute returns value of the counter which is incremented when
39+
status query results negative.
40+
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What: /sys/kernel/debug/qat_<device>_<BDF>/heartbeat/queries_sent
42+
Date: November 2023
43+
KernelVersion: 6.6
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Contact: [email protected]
45+
Description: (RO) Read returns the number of times the control process checked
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if the device is responsive.
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Attribute returns value of the counter which is incremented on
49+
every status query.
50+
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What: /sys/kernel/debug/qat_<device>_<BDF>/heartbeat/status
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Date: November 2023
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KernelVersion: 6.6
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Contact: [email protected]
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Description: (RO) Read returns the device health status.
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Returns 0 when device is healthy or -1 when is unresponsive
58+
or the query failed to send.
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The driver does not monitor for Heartbeat. It is left for a user
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to poll the status periodically.

‎Documentation/ABI/testing/sysfs-driver-ccp

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@@ -85,3 +85,21 @@ Description:
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Possible values:
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0: Not enforced
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1: Enforced
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What: /sys/bus/pci/devices/<BDF>/bootloader_version
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Date: June 2023
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KernelVersion: 6.4
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Contact: [email protected]
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Description:
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The /sys/bus/pci/devices/<BDF>/bootloader_version
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file reports the firmware version of the AMD AGESA
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bootloader.
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What: /sys/bus/pci/devices/<BDF>/tee_version
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Date: June 2023
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KernelVersion: 6.4
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Contact: [email protected]
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Description:
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The /sys/bus/pci/devices/<BDF>/tee_version
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file reports the firmware version of the AMD Trusted
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Execution Environment (TEE).

‎Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml

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@@ -20,6 +20,7 @@ properties:
2020
- stericsson,ux500-hash
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- st,stm32f456-hash
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- st,stm32f756-hash
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- st,stm32mp13-hash
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reg:
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maxItems: 1

‎MAINTAINERS

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@@ -915,6 +915,18 @@ S: Supported
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F: drivers/crypto/ccp/sev*
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F: include/uapi/linux/psp-sev.h
917917

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AMD CRYPTOGRAPHIC COPROCESSOR (CCP) DRIVER - DBC SUPPORT
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M: Mario Limonciello <[email protected]>
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L: [email protected]
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S: Supported
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F: drivers/crypto/ccp/dbc.c
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F: drivers/crypto/ccp/dbc.h
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F: drivers/crypto/ccp/platform-access.c
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F: drivers/crypto/ccp/platform-access.h
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F: include/uapi/linux/psp-dbc.h
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F: tools/crypto/ccp/*.c
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F: tools/crypto/ccp/*.py
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918930
AMD DISPLAY CORE
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M: Harry Wentland <[email protected]>
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M: Leo Li <[email protected]>

‎arch/arm64/crypto/Makefile

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@@ -81,11 +81,6 @@ aes-arm64-y := aes-cipher-core.o aes-cipher-glue.o
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obj-$(CONFIG_CRYPTO_AES_ARM64_BS) += aes-neon-bs.o
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aes-neon-bs-y := aes-neonbs-core.o aes-neonbs-glue.o
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84-
CFLAGS_aes-glue-ce.o := -DUSE_V8_CRYPTO_EXTENSIONS
85-
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$(obj)/aes-glue-%.o: $(src)/aes-glue.c FORCE
87-
$(call if_changed_rule,cc_o_c)
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quiet_cmd_perlasm = PERLASM $@
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cmd_perlasm = $(PERL) $(<) void $(@)
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‎arch/arm64/crypto/aes-glue-ce.c

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#define USE_V8_CRYPTO_EXTENSIONS
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#include "aes-glue.c"

‎arch/arm64/crypto/aes-glue-neon.c

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#include "aes-glue.c"

‎arch/powerpc/crypto/Kconfig

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@@ -111,4 +111,30 @@ config CRYPTO_AES_GCM_P10
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Support for cryptographic acceleration instructions on Power10 or
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later CPU. This module supports stitched acceleration for AES/GCM.
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114+
config CRYPTO_CHACHA20_P10
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tristate "Ciphers: ChaCha20, XChacha20, XChacha12 (P10 or later)"
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depends on PPC64 && CPU_LITTLE_ENDIAN
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select CRYPTO_SKCIPHER
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select CRYPTO_LIB_CHACHA_GENERIC
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select CRYPTO_ARCH_HAVE_LIB_CHACHA
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help
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Length-preserving ciphers: ChaCha20, XChaCha20, and XChaCha12
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stream cipher algorithms
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Architecture: PowerPC64
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- Power10 or later
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- Little-endian
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config CRYPTO_POLY1305_P10
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tristate "Hash functions: Poly1305 (P10 or later)"
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depends on PPC64 && CPU_LITTLE_ENDIAN
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select CRYPTO_HASH
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select CRYPTO_LIB_POLY1305_GENERIC
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help
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Poly1305 authenticator algorithm (RFC7539)
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Architecture: PowerPC64
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- Power10 or later
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- Little-endian
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endmenu

‎arch/powerpc/crypto/Makefile

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@@ -14,6 +14,8 @@ obj-$(CONFIG_CRYPTO_CRC32C_VPMSUM) += crc32c-vpmsum.o
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obj-$(CONFIG_CRYPTO_CRCT10DIF_VPMSUM) += crct10dif-vpmsum.o
1515
obj-$(CONFIG_CRYPTO_VPMSUM_TESTER) += crc-vpmsum_test.o
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obj-$(CONFIG_CRYPTO_AES_GCM_P10) += aes-gcm-p10-crypto.o
17+
obj-$(CONFIG_CRYPTO_CHACHA20_P10) += chacha-p10-crypto.o
18+
obj-$(CONFIG_CRYPTO_POLY1305_P10) += poly1305-p10-crypto.o
1719

1820
aes-ppc-spe-y := aes-spe-core.o aes-spe-keys.o aes-tab-4k.o aes-spe-modes.o aes-spe-glue.o
1921
md5-ppc-y := md5-asm.o md5-glue.o
@@ -23,6 +25,8 @@ sha256-ppc-spe-y := sha256-spe-asm.o sha256-spe-glue.o
2325
crc32c-vpmsum-y := crc32c-vpmsum_asm.o crc32c-vpmsum_glue.o
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crct10dif-vpmsum-y := crct10dif-vpmsum_asm.o crct10dif-vpmsum_glue.o
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aes-gcm-p10-crypto-y := aes-gcm-p10-glue.o aes-gcm-p10.o ghashp10-ppc.o aesp10-ppc.o
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chacha-p10-crypto-y := chacha-p10-glue.o chacha-p10le-8x.o
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poly1305-p10-crypto-y := poly1305-p10-glue.o poly1305-p10le_64.o
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quiet_cmd_perl = PERL $@
2832
cmd_perl = $(PERL) $< $(if $(CONFIG_CPU_LITTLE_ENDIAN), linux-ppc64le, linux-ppc64) > $@

‎arch/powerpc/crypto/chacha-p10-glue.c

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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
3+
* PowerPC P10 (ppc64le) accelerated ChaCha and XChaCha stream ciphers,
4+
* including ChaCha20 (RFC7539)
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*
6+
* Copyright 2023- IBM Corp. All rights reserved.
7+
*/
8+
9+
#include <crypto/algapi.h>
10+
#include <crypto/internal/chacha.h>
11+
#include <crypto/internal/simd.h>
12+
#include <crypto/internal/skcipher.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/cpufeature.h>
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#include <linux/sizes.h>
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#include <asm/simd.h>
18+
#include <asm/switch_to.h>
19+
20+
asmlinkage void chacha_p10le_8x(u32 *state, u8 *dst, const u8 *src,
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unsigned int len, int nrounds);
22+
23+
static __ro_after_init DEFINE_STATIC_KEY_FALSE(have_p10);
24+
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static void vsx_begin(void)
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{
27+
preempt_disable();
28+
enable_kernel_vsx();
29+
}
30+
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static void vsx_end(void)
32+
{
33+
disable_kernel_vsx();
34+
preempt_enable();
35+
}
36+
37+
static void chacha_p10_do_8x(u32 *state, u8 *dst, const u8 *src,
38+
unsigned int bytes, int nrounds)
39+
{
40+
unsigned int l = bytes & ~0x0FF;
41+
42+
if (l > 0) {
43+
chacha_p10le_8x(state, dst, src, l, nrounds);
44+
bytes -= l;
45+
src += l;
46+
dst += l;
47+
state[12] += l / CHACHA_BLOCK_SIZE;
48+
}
49+
50+
if (bytes > 0)
51+
chacha_crypt_generic(state, dst, src, bytes, nrounds);
52+
}
53+
54+
void hchacha_block_arch(const u32 *state, u32 *stream, int nrounds)
55+
{
56+
hchacha_block_generic(state, stream, nrounds);
57+
}
58+
EXPORT_SYMBOL(hchacha_block_arch);
59+
60+
void chacha_init_arch(u32 *state, const u32 *key, const u8 *iv)
61+
{
62+
chacha_init_generic(state, key, iv);
63+
}
64+
EXPORT_SYMBOL(chacha_init_arch);
65+
66+
void chacha_crypt_arch(u32 *state, u8 *dst, const u8 *src, unsigned int bytes,
67+
int nrounds)
68+
{
69+
if (!static_branch_likely(&have_p10) || bytes <= CHACHA_BLOCK_SIZE ||
70+
!crypto_simd_usable())
71+
return chacha_crypt_generic(state, dst, src, bytes, nrounds);
72+
73+
do {
74+
unsigned int todo = min_t(unsigned int, bytes, SZ_4K);
75+
76+
vsx_begin();
77+
chacha_p10_do_8x(state, dst, src, todo, nrounds);
78+
vsx_end();
79+
80+
bytes -= todo;
81+
src += todo;
82+
dst += todo;
83+
} while (bytes);
84+
}
85+
EXPORT_SYMBOL(chacha_crypt_arch);
86+
87+
static int chacha_p10_stream_xor(struct skcipher_request *req,
88+
const struct chacha_ctx *ctx, const u8 *iv)
89+
{
90+
struct skcipher_walk walk;
91+
u32 state[16];
92+
int err;
93+
94+
err = skcipher_walk_virt(&walk, req, false);
95+
if (err)
96+
return err;
97+
98+
chacha_init_generic(state, ctx->key, iv);
99+
100+
while (walk.nbytes > 0) {
101+
unsigned int nbytes = walk.nbytes;
102+
103+
if (nbytes < walk.total)
104+
nbytes = rounddown(nbytes, walk.stride);
105+
106+
if (!crypto_simd_usable()) {
107+
chacha_crypt_generic(state, walk.dst.virt.addr,
108+
walk.src.virt.addr, nbytes,
109+
ctx->nrounds);
110+
} else {
111+
vsx_begin();
112+
chacha_p10_do_8x(state, walk.dst.virt.addr,
113+
walk.src.virt.addr, nbytes, ctx->nrounds);
114+
vsx_end();
115+
}
116+
err = skcipher_walk_done(&walk, walk.nbytes - nbytes);
117+
if (err)
118+
break;
119+
}
120+
121+
return err;
122+
}
123+
124+
static int chacha_p10(struct skcipher_request *req)
125+
{
126+
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
127+
struct chacha_ctx *ctx = crypto_skcipher_ctx(tfm);
128+
129+
return chacha_p10_stream_xor(req, ctx, req->iv);
130+
}
131+
132+
static int xchacha_p10(struct skcipher_request *req)
133+
{
134+
struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
135+
struct chacha_ctx *ctx = crypto_skcipher_ctx(tfm);
136+
struct chacha_ctx subctx;
137+
u32 state[16];
138+
u8 real_iv[16];
139+
140+
chacha_init_generic(state, ctx->key, req->iv);
141+
hchacha_block_arch(state, subctx.key, ctx->nrounds);
142+
subctx.nrounds = ctx->nrounds;
143+
144+
memcpy(&real_iv[0], req->iv + 24, 8);
145+
memcpy(&real_iv[8], req->iv + 16, 8);
146+
return chacha_p10_stream_xor(req, &subctx, real_iv);
147+
}
148+
149+
static struct skcipher_alg algs[] = {
150+
{
151+
.base.cra_name = "chacha20",
152+
.base.cra_driver_name = "chacha20-p10",
153+
.base.cra_priority = 300,
154+
.base.cra_blocksize = 1,
155+
.base.cra_ctxsize = sizeof(struct chacha_ctx),
156+
.base.cra_module = THIS_MODULE,
157+
158+
.min_keysize = CHACHA_KEY_SIZE,
159+
.max_keysize = CHACHA_KEY_SIZE,
160+
.ivsize = CHACHA_IV_SIZE,
161+
.chunksize = CHACHA_BLOCK_SIZE,
162+
.setkey = chacha20_setkey,
163+
.encrypt = chacha_p10,
164+
.decrypt = chacha_p10,
165+
}, {
166+
.base.cra_name = "xchacha20",
167+
.base.cra_driver_name = "xchacha20-p10",
168+
.base.cra_priority = 300,
169+
.base.cra_blocksize = 1,
170+
.base.cra_ctxsize = sizeof(struct chacha_ctx),
171+
.base.cra_module = THIS_MODULE,
172+
173+
.min_keysize = CHACHA_KEY_SIZE,
174+
.max_keysize = CHACHA_KEY_SIZE,
175+
.ivsize = XCHACHA_IV_SIZE,
176+
.chunksize = CHACHA_BLOCK_SIZE,
177+
.setkey = chacha20_setkey,
178+
.encrypt = xchacha_p10,
179+
.decrypt = xchacha_p10,
180+
}, {
181+
.base.cra_name = "xchacha12",
182+
.base.cra_driver_name = "xchacha12-p10",
183+
.base.cra_priority = 300,
184+
.base.cra_blocksize = 1,
185+
.base.cra_ctxsize = sizeof(struct chacha_ctx),
186+
.base.cra_module = THIS_MODULE,
187+
188+
.min_keysize = CHACHA_KEY_SIZE,
189+
.max_keysize = CHACHA_KEY_SIZE,
190+
.ivsize = XCHACHA_IV_SIZE,
191+
.chunksize = CHACHA_BLOCK_SIZE,
192+
.setkey = chacha12_setkey,
193+
.encrypt = xchacha_p10,
194+
.decrypt = xchacha_p10,
195+
}
196+
};
197+
198+
static int __init chacha_p10_init(void)
199+
{
200+
static_branch_enable(&have_p10);
201+
202+
return crypto_register_skciphers(algs, ARRAY_SIZE(algs));
203+
}
204+
205+
static void __exit chacha_p10_exit(void)
206+
{
207+
crypto_unregister_skciphers(algs, ARRAY_SIZE(algs));
208+
}
209+
210+
module_cpu_feature_match(PPC_MODULE_FEATURE_P10, chacha_p10_init);
211+
module_exit(chacha_p10_exit);
212+
213+
MODULE_DESCRIPTION("ChaCha and XChaCha stream ciphers (P10 accelerated)");
214+
MODULE_AUTHOR("Danny Tsen <[email protected]>");
215+
MODULE_LICENSE("GPL v2");
216+
MODULE_ALIAS_CRYPTO("chacha20");
217+
MODULE_ALIAS_CRYPTO("chacha20-p10");
218+
MODULE_ALIAS_CRYPTO("xchacha20");
219+
MODULE_ALIAS_CRYPTO("xchacha20-p10");
220+
MODULE_ALIAS_CRYPTO("xchacha12");
221+
MODULE_ALIAS_CRYPTO("xchacha12-p10");

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