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Biao Huangdavem330
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net: ethernet: mtk-star-emac: add support for MT8365 SoC
Add Ethernet driver support for MT8365 SoC. Signed-off-by: Biao Huang <[email protected]> Signed-off-by: Yinghua Pan <[email protected]> Signed-off-by: Fabien Parent <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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drivers/net/ethernet/mediatek/mtk_star_emac.c

Lines changed: 64 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -150,6 +150,7 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" };
150150
#define MTK_STAR_REG_MAC_CLK_CONF 0x00ac
151151
#define MTK_STAR_MSK_MAC_CLK_CONF GENMASK(7, 0)
152152
#define MTK_STAR_BIT_CLK_DIV_10 0x0a
153+
#define MTK_STAR_BIT_CLK_DIV_50 0x32
153154

154155
/* Counter registers. */
155156
#define MTK_STAR_REG_C_RXOKPKT 0x0100
@@ -182,9 +183,11 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" };
182183
#define MTK_STAR_REG_C_RX_TWIST 0x0218
183184

184185
/* Ethernet CFG Control */
185-
#define MTK_PERICFG_REG_NIC_CFG_CON 0x03c4
186-
#define MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII GENMASK(3, 0)
187-
#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII BIT(0)
186+
#define MTK_PERICFG_REG_NIC_CFG0_CON 0x03c4
187+
#define MTK_PERICFG_REG_NIC_CFG1_CON 0x03c8
188+
#define MTK_PERICFG_REG_NIC_CFG_CON_V2 0x0c10
189+
#define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0)
190+
#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII 1
188191

189192
/* Represents the actual structure of descriptors used by the MAC. We can
190193
* reuse the same structure for both TX and RX - the layout is the same, only
@@ -233,6 +236,7 @@ struct mtk_star_ring {
233236
};
234237

235238
struct mtk_star_compat {
239+
int (*set_interface_mode)(struct net_device *ndev);
236240
unsigned char bit_clk_div;
237241
};
238242

@@ -908,13 +912,6 @@ static void mtk_star_init_config(struct mtk_star_priv *priv)
908912
priv->compat_data->bit_clk_div);
909913
}
910914

911-
static void mtk_star_set_mode_rmii(struct mtk_star_priv *priv)
912-
{
913-
regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG_CON,
914-
MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII,
915-
MTK_PERICFG_BIT_NIC_CFG_CON_RMII);
916-
}
917-
918915
static int mtk_star_enable(struct net_device *ndev)
919916
{
920917
struct mtk_star_priv *priv = netdev_priv(ndev);
@@ -1530,7 +1527,13 @@ static int mtk_star_probe(struct platform_device *pdev)
15301527
return -ENODEV;
15311528
}
15321529

1533-
mtk_star_set_mode_rmii(priv);
1530+
if (priv->compat_data->set_interface_mode) {
1531+
ret = priv->compat_data->set_interface_mode(ndev);
1532+
if (ret) {
1533+
dev_err(dev, "Failed to set phy interface, err = %d\n", ret);
1534+
return -EINVAL;
1535+
}
1536+
}
15341537

15351538
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
15361539
if (ret) {
@@ -1564,17 +1567,67 @@ static int mtk_star_probe(struct platform_device *pdev)
15641567
}
15651568

15661569
#ifdef CONFIG_OF
1570+
static int mt8516_set_interface_mode(struct net_device *ndev)
1571+
{
1572+
struct mtk_star_priv *priv = netdev_priv(ndev);
1573+
struct device *dev = mtk_star_get_dev(priv);
1574+
unsigned int intf_val;
1575+
1576+
switch (priv->phy_intf) {
1577+
case PHY_INTERFACE_MODE_RMII:
1578+
intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII;
1579+
break;
1580+
default:
1581+
dev_err(dev, "This interface not supported\n");
1582+
return -EINVAL;
1583+
}
1584+
1585+
return regmap_update_bits(priv->pericfg,
1586+
MTK_PERICFG_REG_NIC_CFG0_CON,
1587+
MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF,
1588+
intf_val);
1589+
}
1590+
1591+
static int mt8365_set_interface_mode(struct net_device *ndev)
1592+
{
1593+
struct mtk_star_priv *priv = netdev_priv(ndev);
1594+
struct device *dev = mtk_star_get_dev(priv);
1595+
unsigned int intf_val;
1596+
1597+
switch (priv->phy_intf) {
1598+
case PHY_INTERFACE_MODE_RMII:
1599+
intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII;
1600+
break;
1601+
default:
1602+
dev_err(dev, "This interface not supported\n");
1603+
return -EINVAL;
1604+
}
1605+
1606+
return regmap_update_bits(priv->pericfg,
1607+
MTK_PERICFG_REG_NIC_CFG_CON_V2,
1608+
MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF,
1609+
intf_val);
1610+
}
1611+
15671612
static const struct mtk_star_compat mtk_star_mt8516_compat = {
1613+
.set_interface_mode = mt8516_set_interface_mode,
15681614
.bit_clk_div = MTK_STAR_BIT_CLK_DIV_10,
15691615
};
15701616

1617+
static const struct mtk_star_compat mtk_star_mt8365_compat = {
1618+
.set_interface_mode = mt8365_set_interface_mode,
1619+
.bit_clk_div = MTK_STAR_BIT_CLK_DIV_50,
1620+
};
1621+
15711622
static const struct of_device_id mtk_star_of_match[] = {
15721623
{ .compatible = "mediatek,mt8516-eth",
15731624
.data = &mtk_star_mt8516_compat },
15741625
{ .compatible = "mediatek,mt8518-eth",
15751626
.data = &mtk_star_mt8516_compat },
15761627
{ .compatible = "mediatek,mt8175-eth",
15771628
.data = &mtk_star_mt8516_compat },
1629+
{ .compatible = "mediatek,mt8365-eth",
1630+
.data = &mtk_star_mt8365_compat },
15781631
{ }
15791632
};
15801633
MODULE_DEVICE_TABLE(of, mtk_star_of_match);

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