@@ -150,6 +150,7 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" };
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#define MTK_STAR_REG_MAC_CLK_CONF 0x00ac
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#define MTK_STAR_MSK_MAC_CLK_CONF GENMASK(7, 0)
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#define MTK_STAR_BIT_CLK_DIV_10 0x0a
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+ #define MTK_STAR_BIT_CLK_DIV_50 0x32
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/* Counter registers. */
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#define MTK_STAR_REG_C_RXOKPKT 0x0100
@@ -182,9 +183,11 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" };
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#define MTK_STAR_REG_C_RX_TWIST 0x0218
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/* Ethernet CFG Control */
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- #define MTK_PERICFG_REG_NIC_CFG_CON 0x03c4
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- #define MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII GENMASK(3, 0)
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- #define MTK_PERICFG_BIT_NIC_CFG_CON_RMII BIT(0)
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+ #define MTK_PERICFG_REG_NIC_CFG0_CON 0x03c4
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+ #define MTK_PERICFG_REG_NIC_CFG1_CON 0x03c8
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+ #define MTK_PERICFG_REG_NIC_CFG_CON_V2 0x0c10
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+ #define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0)
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+ #define MTK_PERICFG_BIT_NIC_CFG_CON_RMII 1
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/* Represents the actual structure of descriptors used by the MAC. We can
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* reuse the same structure for both TX and RX - the layout is the same, only
@@ -233,6 +236,7 @@ struct mtk_star_ring {
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};
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struct mtk_star_compat {
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+ int (* set_interface_mode )(struct net_device * ndev );
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unsigned char bit_clk_div ;
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};
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@@ -908,13 +912,6 @@ static void mtk_star_init_config(struct mtk_star_priv *priv)
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priv -> compat_data -> bit_clk_div );
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}
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- static void mtk_star_set_mode_rmii (struct mtk_star_priv * priv )
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- {
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- regmap_update_bits (priv -> pericfg , MTK_PERICFG_REG_NIC_CFG_CON ,
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- MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII ,
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- MTK_PERICFG_BIT_NIC_CFG_CON_RMII );
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- }
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-
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static int mtk_star_enable (struct net_device * ndev )
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{
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struct mtk_star_priv * priv = netdev_priv (ndev );
@@ -1530,7 +1527,13 @@ static int mtk_star_probe(struct platform_device *pdev)
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return - ENODEV ;
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}
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- mtk_star_set_mode_rmii (priv );
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+ if (priv -> compat_data -> set_interface_mode ) {
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+ ret = priv -> compat_data -> set_interface_mode (ndev );
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+ if (ret ) {
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+ dev_err (dev , "Failed to set phy interface, err = %d\n" , ret );
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+ return - EINVAL ;
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+ }
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+ }
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ret = dma_set_mask_and_coherent (dev , DMA_BIT_MASK (32 ));
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if (ret ) {
@@ -1564,17 +1567,67 @@ static int mtk_star_probe(struct platform_device *pdev)
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}
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#ifdef CONFIG_OF
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+ static int mt8516_set_interface_mode (struct net_device * ndev )
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+ {
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+ struct mtk_star_priv * priv = netdev_priv (ndev );
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+ struct device * dev = mtk_star_get_dev (priv );
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+ unsigned int intf_val ;
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+
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+ switch (priv -> phy_intf ) {
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+ case PHY_INTERFACE_MODE_RMII :
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+ intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII ;
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+ break ;
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+ default :
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+ dev_err (dev , "This interface not supported\n" );
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+ return - EINVAL ;
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+ }
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+
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+ return regmap_update_bits (priv -> pericfg ,
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+ MTK_PERICFG_REG_NIC_CFG0_CON ,
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+ MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF ,
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+ intf_val );
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+ }
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+
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+ static int mt8365_set_interface_mode (struct net_device * ndev )
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+ {
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+ struct mtk_star_priv * priv = netdev_priv (ndev );
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+ struct device * dev = mtk_star_get_dev (priv );
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+ unsigned int intf_val ;
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+
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+ switch (priv -> phy_intf ) {
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+ case PHY_INTERFACE_MODE_RMII :
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+ intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII ;
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+ break ;
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+ default :
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+ dev_err (dev , "This interface not supported\n" );
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+ return - EINVAL ;
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+ }
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+
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+ return regmap_update_bits (priv -> pericfg ,
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+ MTK_PERICFG_REG_NIC_CFG_CON_V2 ,
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+ MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF ,
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+ intf_val );
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+ }
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+
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static const struct mtk_star_compat mtk_star_mt8516_compat = {
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+ .set_interface_mode = mt8516_set_interface_mode ,
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.bit_clk_div = MTK_STAR_BIT_CLK_DIV_10 ,
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};
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+ static const struct mtk_star_compat mtk_star_mt8365_compat = {
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+ .set_interface_mode = mt8365_set_interface_mode ,
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+ .bit_clk_div = MTK_STAR_BIT_CLK_DIV_50 ,
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+ };
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+
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static const struct of_device_id mtk_star_of_match [] = {
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{ .compatible = "mediatek,mt8516-eth" ,
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.data = & mtk_star_mt8516_compat },
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{ .compatible = "mediatek,mt8518-eth" ,
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.data = & mtk_star_mt8516_compat },
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{ .compatible = "mediatek,mt8175-eth" ,
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.data = & mtk_star_mt8516_compat },
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+ { .compatible = "mediatek,mt8365-eth" ,
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+ .data = & mtk_star_mt8365_compat },
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{ }
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};
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MODULE_DEVICE_TABLE (of , mtk_star_of_match );
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