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Niravkumar L Rabarabp3tk0v
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EDAC/altera: Set DDR and SDMMC interrupt mask before registration
Mask DDR and SDMMC in probe function to avoid spurious interrupts before registration. Removed invalid register write to system manager. Fixes: 1166fde ("EDAC, altera: Add Arria10 ECC memory init functions") Signed-off-by: Niravkumar L Rabara <[email protected]> Signed-off-by: Matthew Gerlach <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Acked-by: Dinh Nguyen <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/[email protected]
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-3
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+6
-3
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drivers/edac/altera_edac.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1005,9 +1005,6 @@ altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
10051005
}
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}
10071007

1008-
/* Interrupt mode set to every SBERR */
1009-
regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
1010-
ALTR_A10_ECC_INTMODE);
10111008
/* Enable ECC */
10121009
ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
10131010
ALTR_A10_ECC_CTRL_OFST));
@@ -2127,6 +2124,10 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
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return PTR_ERR(edac->ecc_mgr_map);
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}
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2127+
/* Set irq mask for DDR SBE to avoid any pending irq before registration */
2128+
regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
2129+
(A10_SYSMGR_ECC_INTMASK_SDMMCB | A10_SYSMGR_ECC_INTMASK_DDR0));
2130+
21302131
edac->irq_chip.name = pdev->dev.of_node->name;
21312132
edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
21322133
edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;

drivers/edac/altera_edac.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -249,6 +249,8 @@ struct altr_sdram_mc_data {
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#define A10_SYSMGR_ECC_INTMASK_SET_OFST 0x94
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#define A10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98
251251
#define A10_SYSMGR_ECC_INTMASK_OCRAM BIT(1)
252+
#define A10_SYSMGR_ECC_INTMASK_SDMMCB BIT(16)
253+
#define A10_SYSMGR_ECC_INTMASK_DDR0 BIT(17)
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253255
#define A10_SYSMGR_ECC_INTSTAT_SERR_OFST 0x9C
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#define A10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xA0

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