Skip to content

Commit 701016c

Browse files
Srinivas-Kandagatlabroonie
Srinivas-Kandagatla
authored and
broonie
committed
pinctrl: st: Add pinctrl and pinconf support.
This patch add pinctrl support to ST SoCs. About hardware: ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle pin configurations. Each multi-function pin is controlled, driven and routed through the PIO multiplexing block. Each pin supports GPIO functionality (ALT0) and multiple alternate functions(ALT1 - ALTx) that directly connect the pin to different hardware blocks. When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and Pull Up (PU) are driven by the related PIO block. Otherwise the PIO multiplexing block configures these parameters and retiming the signal. About driver: This pinctrl driver manages both PIO and PIO-mux block using pinctrl, pinconf, pinmux, gpio subsystems. All the pinctrl related config information can only come from device trees. Signed-off-by: Srinivas Kandagatla <[email protected]> Acked-by: Linus Walleij <[email protected]> Signed-off-by: Mark Brown <[email protected]>
1 parent 6725228 commit 701016c

File tree

4 files changed

+1520
-0
lines changed

4 files changed

+1520
-0
lines changed

‎Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt

Lines changed: 110 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,110 @@
1+
*ST pin controller.
2+
3+
Each multi-function pin is controlled, driven and routed through the
4+
PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
5+
and multiple alternate functions(ALT1 - ALTx) that directly connect
6+
the pin to different hardware blocks.
7+
8+
When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
9+
Pull Up (PU) are driven by the related PIO block.
10+
11+
ST pinctrl driver controls PIO multiplexing block and also interacts with
12+
gpio driver to configure a pin.
13+
14+
Required properties: (PIO multiplexing block)
15+
- compatible : should be "st,<SOC>-<pio-block>-pinctrl"
16+
like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on.
17+
- gpio-controller : Indicates this device is a GPIO controller
18+
- #gpio-cells : Should be one. The first cell is the pin number.
19+
- st,retime-pin-mask : Should be mask to specify which pins can be retimed.
20+
If the property is not present, it is assumed that all the pins in the
21+
bank are capable of retiming. Retiming is mainly used to improve the
22+
IO timing margins of external synchronous interfaces.
23+
- st,bank-name : Should be a name string for this bank as
24+
specified in datasheet.
25+
- st,syscfg : Should be a phandle of the syscfg node.
26+
27+
Example:
28+
pin-controller-sbc {
29+
#address-cells = <1>;
30+
#size-cells = <1>;
31+
compatible = "st,stih415-sbc-pinctrl";
32+
st,syscfg = <&syscfg_sbc>;
33+
ranges = <0 0xfe610000 0x5000>;
34+
PIO0: gpio@fe610000 {
35+
gpio-controller;
36+
#gpio-cells = <1>;
37+
reg = <0 0x100>;
38+
st,bank-name = "PIO0";
39+
};
40+
...
41+
pin-functions nodes follow...
42+
};
43+
44+
45+
Contents of function subnode node:
46+
----------------------
47+
Required properties for pin configuration node:
48+
- st,pins : Child node with list of pins with configuration.
49+
50+
Below is the format of how each pin conf should look like.
51+
52+
<bank offset mux mode rt_type rt_delay rt_clk>
53+
54+
Every PIO is represented with 4-7 parameters depending on retime configuration.
55+
Each parameter is explained as below.
56+
57+
-bank : Should be bank phandle to which this PIO belongs.
58+
-offset : Offset in the PIO bank.
59+
-mux : Should be alternate function number associated this pin.
60+
Use same numbers from datasheet.
61+
-mode :pin configuration is selected from one of the below values.
62+
IN
63+
IN_PU
64+
OUT
65+
BIDIR
66+
BIDIR_PU
67+
68+
-rt_type Retiming Configuration for the pin.
69+
Possible retime configuration are:
70+
71+
------- -------------
72+
value args
73+
------- -------------
74+
NICLK <delay> <clk>
75+
ICLK_IO <delay> <clk>
76+
BYPASS <delay>
77+
DE_IO <delay> <clk>
78+
SE_ICLK_IO <delay> <clk>
79+
SE_NICLK_IO <delay> <clk>
80+
81+
- delay is retime delay in pico seconds as mentioned in data sheet.
82+
83+
- rt_clk :clk to be use for retime.
84+
Possible values are:
85+
CLK_A
86+
CLK_B
87+
CLK_C
88+
CLK_D
89+
90+
Example of mmcclk pin which is a bi-direction pull pu with retime config
91+
as non inverted clock retimed with CLK_B and delay of 0 pico seconds:
92+
93+
pin-controller {
94+
...
95+
mmc0 {
96+
pinctrl_mmc: mmc {
97+
st,pins {
98+
mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
99+
...
100+
};
101+
};
102+
...
103+
};
104+
};
105+
106+
sdhci0:sdhci@fe810000{
107+
...
108+
pinctrl-names = "default";
109+
pinctrl-0 = <&pinctrl_mmc>;
110+
};

‎drivers/pinctrl/Kconfig

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -169,6 +169,12 @@ config PINCTRL_SUNXI
169169
select PINMUX
170170
select GENERIC_PINCONF
171171

172+
config PINCTRL_ST
173+
bool
174+
depends on OF
175+
select PINMUX
176+
select PINCONF
177+
172178
config PINCTRL_TEGRA
173179
bool
174180
select PINMUX

‎drivers/pinctrl/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o
4545
obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
4646
obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
4747
obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
48+
obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
4849

4950
obj-$(CONFIG_PLAT_ORION) += mvebu/
5051
obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/

0 commit comments

Comments
 (0)