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kuba-mookuba-moo
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Merge branch 'stmmac-ETF-support'
Jose Abreu says: ==================== net: stmmac: ETF support This series adds the support for ETF scheduler in stmmac. 1) Starts adding the support by implementing Enhanced Descriptors in stmmac main core. This is needed for ETF feature in XGMAC and QoS cores. 2) Integrates the ETF logic into stmmac TC core. 3) and 4) adds the HW specific support for ETF in XGMAC and QoS cores. The IP feature is called TBS (Time Based Scheduling). 5) Enables ETF in GMAC5 IPK PCI entry for all Queues except Queue 0. 6) Adds the new TBS feature and even more information into the debugFS HW features file. ==================== Signed-off-by: Jakub Kicinski <[email protected]>
2 parents ab9837b + 28c1cf7 commit 76ccf52

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17 files changed

+362
-84
lines changed

17 files changed

+362
-84
lines changed

‎drivers/net/ethernet/stmicro/stmmac/common.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -368,6 +368,7 @@ struct dma_features {
368368
unsigned int estdep;
369369
unsigned int estsel;
370370
unsigned int fpesel;
371+
unsigned int tbssel;
371372
};
372373

373374
/* RX Buffer size must be multiple of 4/8/16 bytes */

‎drivers/net/ethernet/stmicro/stmmac/descs.h

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -171,6 +171,15 @@ struct dma_extended_desc {
171171
__le32 des7; /* Tx/Rx Timestamp High */
172172
};
173173

174+
/* Enhanced descriptor for TBS */
175+
struct dma_edesc {
176+
__le32 des4;
177+
__le32 des5;
178+
__le32 des6;
179+
__le32 des7;
180+
struct dma_desc basic;
181+
};
182+
174183
/* Transmit checksum insertion control */
175184
#define TX_CIC_FULL 3 /* Include IP header and pseudoheader */
176185

‎drivers/net/ethernet/stmicro/stmmac/dwmac4.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -239,6 +239,7 @@ enum power_event {
239239

240240
/* MAC HW features3 bitmap */
241241
#define GMAC_HW_FEAT_ASP GENMASK(29, 28)
242+
#define GMAC_HW_FEAT_TBSSEL BIT(27)
242243
#define GMAC_HW_FEAT_FPESEL BIT(26)
243244
#define GMAC_HW_FEAT_ESTWID GENMASK(21, 20)
244245
#define GMAC_HW_FEAT_ESTDEP GENMASK(19, 17)

‎drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
1010

1111
#include <linux/stmmac.h>
1212
#include "common.h"
13+
#include "dwmac4.h"
1314
#include "dwmac4_descs.h"
1415

1516
static int dwmac4_wrback_get_tx_status(void *data, struct stmmac_extra_stats *x,
@@ -505,6 +506,14 @@ static void dwmac4_set_sec_addr(struct dma_desc *p, dma_addr_t addr)
505506
p->des3 = cpu_to_le32(upper_32_bits(addr) | RDES3_BUFFER2_VALID_ADDR);
506507
}
507508

509+
static void dwmac4_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)
510+
{
511+
p->des4 = cpu_to_le32((sec & TDES4_LT) | TDES4_LTV);
512+
p->des5 = cpu_to_le32(nsec & TDES5_LT);
513+
p->des6 = 0;
514+
p->des7 = 0;
515+
}
516+
508517
const struct stmmac_desc_ops dwmac4_desc_ops = {
509518
.tx_status = dwmac4_wrback_get_tx_status,
510519
.rx_status = dwmac4_wrback_get_rx_status,
@@ -534,6 +543,7 @@ const struct stmmac_desc_ops dwmac4_desc_ops = {
534543
.set_vlan = dwmac4_set_vlan,
535544
.get_rx_header_len = dwmac4_get_rx_header_len,
536545
.set_sec_addr = dwmac4_set_sec_addr,
546+
.set_tbs = dwmac4_set_tbs,
537547
};
538548

539549
const struct stmmac_mode_ops dwmac4_ring_mode_ops = {

‎drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,13 @@
7373
#define TDES3_CONTEXT_TYPE BIT(30)
7474
#define TDES3_CONTEXT_TYPE_SHIFT 30
7575

76+
/* TDES4 */
77+
#define TDES4_LTV BIT(31)
78+
#define TDES4_LT GENMASK(7, 0)
79+
80+
/* TDES5 */
81+
#define TDES5_LT GENMASK(31, 8)
82+
7683
/* TDS3 use for both format (read and write back) */
7784
#define TDES3_OWN BIT(31)
7885
#define TDES3_OWN_SHIFT 31

‎drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -404,6 +404,7 @@ static void dwmac4_get_hw_feature(void __iomem *ioaddr,
404404

405405
/* 5.10 Features */
406406
dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;
407+
dma_cap->tbssel = (hw_cap & GMAC_HW_FEAT_TBSSEL) >> 27;
407408
dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26;
408409
dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20;
409410
dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17;
@@ -471,6 +472,25 @@ static void dwmac4_enable_sph(void __iomem *ioaddr, bool en, u32 chan)
471472
writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
472473
}
473474

475+
static int dwmac4_enable_tbs(void __iomem *ioaddr, bool en, u32 chan)
476+
{
477+
u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
478+
479+
if (en)
480+
value |= DMA_CONTROL_EDSE;
481+
else
482+
value &= ~DMA_CONTROL_EDSE;
483+
484+
writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
485+
486+
value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)) & DMA_CONTROL_EDSE;
487+
if (en && !value)
488+
return -EIO;
489+
490+
writel(DMA_TBS_DEF_FTOS, ioaddr + DMA_TBS_CTRL);
491+
return 0;
492+
}
493+
474494
const struct stmmac_dma_ops dwmac4_dma_ops = {
475495
.reset = dwmac4_dma_reset,
476496
.init = dwmac4_dma_init,
@@ -527,4 +547,5 @@ const struct stmmac_dma_ops dwmac410_dma_ops = {
527547
.qmode = dwmac4_qmode,
528548
.set_bfsize = dwmac4_set_bfsize,
529549
.enable_sph = dwmac4_enable_sph,
550+
.enable_tbs = dwmac4_enable_tbs,
530551
};

‎drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@
2222
#define DMA_DEBUG_STATUS_1 0x00001010
2323
#define DMA_DEBUG_STATUS_2 0x00001014
2424
#define DMA_AXI_BUS_MODE 0x00001028
25+
#define DMA_TBS_CTRL 0x00001050
2526

2627
/* DMA Bus Mode bitmap */
2728
#define DMA_BUS_MODE_SFT_RESET BIT(0)
@@ -82,6 +83,11 @@
8283

8384
#define DMA_AXI_BURST_LEN_MASK 0x000000FE
8485

86+
/* DMA TBS Control */
87+
#define DMA_TBS_FTOS GENMASK(31, 8)
88+
#define DMA_TBS_FTOV BIT(0)
89+
#define DMA_TBS_DEF_FTOS (DMA_TBS_FTOS | DMA_TBS_FTOV)
90+
8591
/* Following DMA defines are chanels oriented */
8692
#define DMA_CHAN_BASE_ADDR 0x00001100
8793
#define DMA_CHAN_BASE_OFFSET 0x80
@@ -114,6 +120,7 @@
114120
#define DMA_CONTROL_MSS_MASK GENMASK(13, 0)
115121

116122
/* DMA Tx Channel X Control register defines */
123+
#define DMA_CONTROL_EDSE BIT(28)
117124
#define DMA_CONTROL_TSE BIT(12)
118125
#define DMA_CONTROL_OSP BIT(4)
119126
#define DMA_CONTROL_ST BIT(0)

‎drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -139,6 +139,7 @@
139139
#define XGMAC_HWFEAT_TXQCNT GENMASK(9, 6)
140140
#define XGMAC_HWFEAT_RXQCNT GENMASK(3, 0)
141141
#define XGMAC_HW_FEATURE3 0x00000128
142+
#define XGMAC_HWFEAT_TBSSEL BIT(27)
142143
#define XGMAC_HWFEAT_FPESEL BIT(26)
143144
#define XGMAC_HWFEAT_ESTWID GENMASK(24, 23)
144145
#define XGMAC_HWFEAT_ESTDEP GENMASK(22, 20)
@@ -346,6 +347,13 @@
346347
#define XGMAC_TDPS GENMASK(29, 0)
347348
#define XGMAC_RX_EDMA_CTRL 0x00003044
348349
#define XGMAC_RDPS GENMASK(29, 0)
350+
#define XGMAC_DMA_TBS_CTRL0 0x00003054
351+
#define XGMAC_DMA_TBS_CTRL1 0x00003058
352+
#define XGMAC_DMA_TBS_CTRL2 0x0000305c
353+
#define XGMAC_DMA_TBS_CTRL3 0x00003060
354+
#define XGMAC_FTOS GENMASK(31, 8)
355+
#define XGMAC_FTOV BIT(0)
356+
#define XGMAC_DEF_FTOS (XGMAC_FTOS | XGMAC_FTOV)
349357
#define XGMAC_DMA_SAFETY_INT_STATUS 0x00003064
350358
#define XGMAC_MCSIS BIT(31)
351359
#define XGMAC_MSUIS BIT(29)
@@ -360,6 +368,7 @@
360368
#define XGMAC_SPH BIT(24)
361369
#define XGMAC_PBLx8 BIT(16)
362370
#define XGMAC_DMA_CH_TX_CONTROL(x) (0x00003104 + (0x80 * (x)))
371+
#define XGMAC_EDSE BIT(28)
363372
#define XGMAC_TxPBL GENMASK(21, 16)
364373
#define XGMAC_TxPBL_SHIFT 16
365374
#define XGMAC_TSE BIT(12)
@@ -404,6 +413,9 @@
404413
#define XGMAC_REGSIZE ((0x0000317c + (0x80 * 15)) / 4)
405414

406415
/* Descriptors */
416+
#define XGMAC_TDES0_LTV BIT(31)
417+
#define XGMAC_TDES0_LT GENMASK(7, 0)
418+
#define XGMAC_TDES1_LT GENMASK(31, 8)
407419
#define XGMAC_TDES2_IVT GENMASK(31, 16)
408420
#define XGMAC_TDES2_IVT_SHIFT 16
409421
#define XGMAC_TDES2_IOC BIT(31)
@@ -422,6 +434,7 @@
422434
#define XGMAC_TDES3_TCMSSV BIT(26)
423435
#define XGMAC_TDES3_SAIC GENMASK(25, 23)
424436
#define XGMAC_TDES3_SAIC_SHIFT 23
437+
#define XGMAC_TDES3_TBSV BIT(24)
425438
#define XGMAC_TDES3_THL GENMASK(22, 19)
426439
#define XGMAC_TDES3_THL_SHIFT 19
427440
#define XGMAC_TDES3_IVTIR GENMASK(19, 18)

‎drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -339,6 +339,14 @@ static void dwxgmac2_set_vlan(struct dma_desc *p, u32 type)
339339
p->des2 |= cpu_to_le32(type & XGMAC_TDES2_VTIR);
340340
}
341341

342+
static void dwxgmac2_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)
343+
{
344+
p->des4 = cpu_to_le32((sec & XGMAC_TDES0_LT) | XGMAC_TDES0_LTV);
345+
p->des5 = cpu_to_le32(nsec & XGMAC_TDES1_LT);
346+
p->des6 = 0;
347+
p->des7 = 0;
348+
}
349+
342350
const struct stmmac_desc_ops dwxgmac210_desc_ops = {
343351
.tx_status = dwxgmac2_get_tx_status,
344352
.rx_status = dwxgmac2_get_rx_status,
@@ -368,4 +376,5 @@ const struct stmmac_desc_ops dwxgmac210_desc_ops = {
368376
.set_sarc = dwxgmac2_set_sarc,
369377
.set_vlan_tag = dwxgmac2_set_vlan_tag,
370378
.set_vlan = dwxgmac2_set_vlan,
379+
.set_tbs = dwxgmac2_set_tbs,
371380
};

‎drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -429,6 +429,7 @@ static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
429429

430430
/* MAC HW feature 3 */
431431
hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3);
432+
dma_cap->tbssel = (hw_cap & XGMAC_HWFEAT_TBSSEL) >> 27;
432433
dma_cap->fpesel = (hw_cap & XGMAC_HWFEAT_FPESEL) >> 26;
433434
dma_cap->estwid = (hw_cap & XGMAC_HWFEAT_ESTWID) >> 23;
434435
dma_cap->estdep = (hw_cap & XGMAC_HWFEAT_ESTDEP) >> 20;
@@ -523,6 +524,28 @@ static void dwxgmac2_enable_sph(void __iomem *ioaddr, bool en, u32 chan)
523524
writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
524525
}
525526

527+
static int dwxgmac2_enable_tbs(void __iomem *ioaddr, bool en, u32 chan)
528+
{
529+
u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
530+
531+
if (en)
532+
value |= XGMAC_EDSE;
533+
else
534+
value &= ~XGMAC_EDSE;
535+
536+
writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
537+
538+
value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)) & XGMAC_EDSE;
539+
if (en && !value)
540+
return -EIO;
541+
542+
writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL0);
543+
writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL1);
544+
writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL2);
545+
writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL3);
546+
return 0;
547+
}
548+
526549
const struct stmmac_dma_ops dwxgmac210_dma_ops = {
527550
.reset = dwxgmac2_dma_reset,
528551
.init = dwxgmac2_dma_init,
@@ -550,4 +573,5 @@ const struct stmmac_dma_ops dwxgmac210_dma_ops = {
550573
.qmode = dwxgmac2_qmode,
551574
.set_bfsize = dwxgmac2_set_bfsize,
552575
.enable_sph = dwxgmac2_enable_sph,
576+
.enable_tbs = dwxgmac2_enable_tbs,
553577
};

‎drivers/net/ethernet/stmicro/stmmac/hwif.h

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@ struct stmmac_extra_stats;
2929
struct stmmac_safety_stats;
3030
struct dma_desc;
3131
struct dma_extended_desc;
32+
struct dma_edesc;
3233

3334
/* Descriptors helpers */
3435
struct stmmac_desc_ops {
@@ -95,6 +96,7 @@ struct stmmac_desc_ops {
9596
void (*set_vlan_tag)(struct dma_desc *p, u16 tag, u16 inner_tag,
9697
u32 inner_type);
9798
void (*set_vlan)(struct dma_desc *p, u32 type);
99+
void (*set_tbs)(struct dma_edesc *p, u32 sec, u32 nsec);
98100
};
99101

100102
#define stmmac_init_rx_desc(__priv, __args...) \
@@ -157,6 +159,8 @@ struct stmmac_desc_ops {
157159
stmmac_do_void_callback(__priv, desc, set_vlan_tag, __args)
158160
#define stmmac_set_desc_vlan(__priv, __args...) \
159161
stmmac_do_void_callback(__priv, desc, set_vlan, __args)
162+
#define stmmac_set_desc_tbs(__priv, __args...) \
163+
stmmac_do_void_callback(__priv, desc, set_tbs, __args)
160164

161165
struct stmmac_dma_cfg;
162166
struct dma_features;
@@ -210,6 +214,7 @@ struct stmmac_dma_ops {
210214
void (*qmode)(void __iomem *ioaddr, u32 channel, u8 qmode);
211215
void (*set_bfsize)(void __iomem *ioaddr, int bfsize, u32 chan);
212216
void (*enable_sph)(void __iomem *ioaddr, bool en, u32 chan);
217+
int (*enable_tbs)(void __iomem *ioaddr, bool en, u32 chan);
213218
};
214219

215220
#define stmmac_reset(__priv, __args...) \
@@ -268,6 +273,8 @@ struct stmmac_dma_ops {
268273
stmmac_do_void_callback(__priv, dma, set_bfsize, __args)
269274
#define stmmac_enable_sph(__priv, __args...) \
270275
stmmac_do_void_callback(__priv, dma, enable_sph, __args)
276+
#define stmmac_enable_tbs(__priv, __args...) \
277+
stmmac_do_callback(__priv, dma, enable_tbs, __args)
271278

272279
struct mac_device_info;
273280
struct net_device;
@@ -526,6 +533,7 @@ struct tc_cls_u32_offload;
526533
struct tc_cbs_qopt_offload;
527534
struct flow_cls_offload;
528535
struct tc_taprio_qopt_offload;
536+
struct tc_etf_qopt_offload;
529537

530538
struct stmmac_tc_ops {
531539
int (*init)(struct stmmac_priv *priv);
@@ -537,6 +545,8 @@ struct stmmac_tc_ops {
537545
struct flow_cls_offload *cls);
538546
int (*setup_taprio)(struct stmmac_priv *priv,
539547
struct tc_taprio_qopt_offload *qopt);
548+
int (*setup_etf)(struct stmmac_priv *priv,
549+
struct tc_etf_qopt_offload *qopt);
540550
};
541551

542552
#define stmmac_tc_init(__priv, __args...) \
@@ -549,6 +559,8 @@ struct stmmac_tc_ops {
549559
stmmac_do_callback(__priv, tc, setup_cls, __args)
550560
#define stmmac_tc_setup_taprio(__priv, __args...) \
551561
stmmac_do_callback(__priv, tc, setup_taprio, __args)
562+
#define stmmac_tc_setup_etf(__priv, __args...) \
563+
stmmac_do_callback(__priv, tc, setup_etf, __args)
552564

553565
struct stmmac_counters;
554566

‎drivers/net/ethernet/stmicro/stmmac/stmmac.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,13 +39,18 @@ struct stmmac_tx_info {
3939
bool is_jumbo;
4040
};
4141

42+
#define STMMAC_TBS_AVAIL BIT(0)
43+
#define STMMAC_TBS_EN BIT(1)
44+
4245
/* Frequently used values are kept adjacent for cache effect */
4346
struct stmmac_tx_queue {
4447
u32 tx_count_frames;
48+
int tbs;
4549
struct timer_list txtimer;
4650
u32 queue_index;
4751
struct stmmac_priv *priv_data;
4852
struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
53+
struct dma_edesc *dma_entx;
4954
struct dma_desc *dma_tx;
5055
struct sk_buff **tx_skbuff;
5156
struct stmmac_tx_info *tx_skbuff_dma;

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