Skip to content

Commit 793445c

Browse files
csyuancnbd168
authored andcommitted
wifi: mt76: mt7996: update register for CFEND_RATE
In newer chipsets, CFEND_RATE setting has been moved to different hw module. Fixes: 98686cd ("wifi: mt76: mt7996: add driver for MediaTek Wi-Fi 7 (802.11be) devices") Signed-off-by: Shayne Chen <[email protected]> Signed-off-by: Felix Fietkau <[email protected]>
1 parent eb1fdb9 commit 793445c

File tree

3 files changed

+10
-8
lines changed

3 files changed

+10
-8
lines changed

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1690,7 +1690,7 @@ void mt7996_mac_set_timing(struct mt7996_phy *phy)
16901690
else
16911691
val = MT7996_CFEND_RATE_11B;
16921692

1693-
mt76_rmw_field(dev, MT_AGG_ACR0(band_idx), MT_AGG_ACR_CFEND_RATE, val);
1693+
mt76_rmw_field(dev, MT_RATE_HRCR0(band_idx), MT_RATE_HRCR0_CFEND_RATE, val);
16941694
mt76_clear(dev, MT_ARB_SCR(band_idx),
16951695
MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
16961696
}

drivers/net/wireless/mediatek/mt76/mt7996/mmio.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@ static const struct __base mt7996_reg_base[] = {
2121
[WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
2222
[WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
2323
[WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
24+
[WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } },
2425
};
2526

2627
static const struct __map mt7996_reg_map[] = {

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@ enum base_rev {
3333
WF_ETBF_BASE,
3434
WF_LPON_BASE,
3535
WF_MIB_BASE,
36+
WF_RATE_BASE,
3637
__MT_REG_BASE_MAX,
3738
};
3839

@@ -235,13 +236,6 @@ enum base_rev {
235236
FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \
236237
FIELD_PREP(MT_WTBL_LMAC_DW, _dw))
237238

238-
/* AGG: band 0(0x820e2000), band 1(0x820f2000), band 2(0x830e2000) */
239-
#define MT_WF_AGG_BASE(_band) __BASE(WF_AGG_BASE, (_band))
240-
#define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs))
241-
242-
#define MT_AGG_ACR0(_band) MT_WF_AGG(_band, 0x054)
243-
#define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0)
244-
245239
/* ARB: band 0(0x820e3000), band 1(0x820f3000), band 2(0x830e3000) */
246240
#define MT_WF_ARB_BASE(_band) __BASE(WF_ARB_BASE, (_band))
247241
#define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs))
@@ -300,6 +294,13 @@ enum base_rev {
300294
#define MT_WF_RMAC_RSVD0(_band) MT_WF_RMAC(_band, 0x03e0)
301295
#define MT_WF_RMAC_RSVD0_EIFS_CLR BIT(21)
302296

297+
/* RATE: band 0(0x820ee000), band 1(0x820fe000), band 2(0x830ee000) */
298+
#define MT_WF_RATE_BASE(_band) __BASE(WF_RATE_BASE, (_band))
299+
#define MT_WF_RATE(_band, ofs) (MT_WF_RATE_BASE(_band) + (ofs))
300+
301+
#define MT_RATE_HRCR0(_band) MT_WF_RATE(_band, 0x050)
302+
#define MT_RATE_HRCR0_CFEND_RATE GENMASK(14, 0)
303+
303304
/* WFDMA0 */
304305
#define MT_WFDMA0_BASE 0xd4000
305306
#define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs))

0 commit comments

Comments
 (0)