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314 | 314 | #define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
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315 | 315 | #define IGC_RCTL_BAM 0x00008000 /* broadcast enable */
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316 | 316 |
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| 317 | +/* Split Replication Receive Control */ |
| 318 | +#define IGC_SRRCTL_TIMESTAMP 0x40000000 |
| 319 | +#define IGC_SRRCTL_TIMER1SEL(timer) (((timer) & 0x3) << 14) |
| 320 | +#define IGC_SRRCTL_TIMER0SEL(timer) (((timer) & 0x3) << 17) |
| 321 | + |
317 | 322 | /* Receive Descriptor bit definitions */
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318 | 323 | #define IGC_RXD_STAT_EOP 0x02 /* End of Packet */
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319 | 324 | #define IGC_RXD_STAT_IXSM 0x04 /* Ignore checksum */
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320 | 325 | #define IGC_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
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321 | 326 | #define IGC_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
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322 | 327 |
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| 328 | +/* Advanced Receive Descriptor bit definitions */ |
| 329 | +#define IGC_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */ |
| 330 | +#define IGC_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */ |
| 331 | + |
323 | 332 | #define IGC_RXDEXT_STATERR_CE 0x01000000
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324 | 333 | #define IGC_RXDEXT_STATERR_SE 0x02000000
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325 | 334 | #define IGC_RXDEXT_STATERR_SEQ 0x04000000
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356 | 365 |
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357 | 366 | #define I225_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */
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358 | 367 | #define I225_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
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| 368 | +#define IGC_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */ |
359 | 369 |
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360 | 370 | /* Time Sync Interrupt Causes */
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361 | 371 | #define IGC_TSICR_SYS_WRAP BIT(0) /* SYSTIM Wrap around. */
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367 | 377 |
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368 | 378 | #define IGC_TSICR_INTERRUPTS IGC_TSICR_TXTS
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369 | 379 |
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| 380 | +/* PTP Queue Filter */ |
| 381 | +#define IGC_ETQF_1588 BIT(30) |
| 382 | + |
| 383 | +#define IGC_FTQF_VF_BP 0x00008000 |
| 384 | +#define IGC_FTQF_1588_TIME_STAMP 0x08000000 |
| 385 | +#define IGC_FTQF_MASK 0xF0000000 |
| 386 | +#define IGC_FTQF_MASK_PROTO_BP 0x10000000 |
| 387 | + |
| 388 | +/* Time Sync Receive Control bit definitions */ |
| 389 | +#define IGC_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ |
| 390 | +#define IGC_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ |
| 391 | +#define IGC_TSYNCRXCTL_TYPE_L2_V2 0x00 |
| 392 | +#define IGC_TSYNCRXCTL_TYPE_L4_V1 0x02 |
| 393 | +#define IGC_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 |
| 394 | +#define IGC_TSYNCRXCTL_TYPE_ALL 0x08 |
| 395 | +#define IGC_TSYNCRXCTL_TYPE_EVENT_V2 0x0A |
| 396 | +#define IGC_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ |
| 397 | +#define IGC_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ |
| 398 | + |
| 399 | +/* Time Sync Receive Configuration */ |
| 400 | +#define IGC_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF |
| 401 | +#define IGC_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 |
| 402 | +#define IGC_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 |
| 403 | + |
| 404 | +/* Immediate Interrupt Receive Extended */ |
| 405 | +#define IGC_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */ |
| 406 | +#define IGC_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ |
| 407 | + |
370 | 408 | /* Receive Checksum Control */
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371 | 409 | #define IGC_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
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372 | 410 | #define IGC_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
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