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aeglsuryasaimadhu
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x86/cpu: Read/save PPIN MSR during initialization
Currently, the PPIN (Protected Processor Inventory Number) MSR is read by every CPU that processes a machine check, CMCI, or just polls machine check banks from a periodic timer. This is not a "fast" MSR, so this adds to overhead of processing errors. Add a new "ppin" field to the cpuinfo_x86 structure. Read and save the PPIN during initialization. Use this copy in mce_setup() instead of reading the MSR. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Borislav Petkov <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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-6
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arch/x86/include/asm/processor.h

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@@ -119,6 +119,8 @@ struct cpuinfo_x86 {
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int x86_cache_mbm_width_offset;
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int x86_power;
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unsigned long loops_per_jiffy;
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/* protected processor identification number */
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u64 ppin;
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/* cpuid returned max cores value: */
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u16 x86_max_cores;
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u16 apicid;

arch/x86/kernel/cpu/common.c

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@@ -91,14 +91,17 @@ DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) = BAD_APICID;
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static struct ppin_info {
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int feature;
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int msr_ppin_ctl;
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int msr_ppin;
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} ppin_info[] = {
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[X86_VENDOR_INTEL] = {
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.feature = X86_FEATURE_INTEL_PPIN,
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.msr_ppin_ctl = MSR_PPIN_CTL,
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.msr_ppin = MSR_PPIN
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},
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[X86_VENDOR_AMD] = {
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.feature = X86_FEATURE_AMD_PPIN,
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.msr_ppin_ctl = MSR_AMD_PPIN_CTL,
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.msr_ppin = MSR_AMD_PPIN
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},
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};
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@@ -153,6 +156,7 @@ static void ppin_init(struct cpuinfo_x86 *c)
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/* Is the enable bit set? */
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if (val & 2UL) {
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c->ppin = __rdmsr(info->msr_ppin);
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set_cpu_cap(c, info->feature);
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return;
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}

arch/x86/kernel/cpu/mce/core.c

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@@ -138,12 +138,7 @@ void mce_setup(struct mce *m)
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m->socketid = cpu_data(m->extcpu).phys_proc_id;
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m->apicid = cpu_data(m->extcpu).initial_apicid;
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m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP);
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if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
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m->ppin = __rdmsr(MSR_PPIN);
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else if (this_cpu_has(X86_FEATURE_AMD_PPIN))
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m->ppin = __rdmsr(MSR_AMD_PPIN);
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m->ppin = cpu_data(m->extcpu).ppin;
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m->microcode = boot_cpu_data.microcode;
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}
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