@@ -46,8 +46,7 @@ MODULE_VERSION(HECC_MODULE_VERSION);
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#define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */
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#define MAX_TX_PRIO 0x3F /* hardware value - do not change */
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- /*
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- * Important Note: TX mailbox configuration
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+ /* Important Note: TX mailbox configuration
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* TX mailboxes should be restricted to the number of SKB buffers to avoid
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* maintaining SKB buffers separately. TX mailboxes should be a power of 2
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* for the mailbox logic to work. Top mailbox numbers are reserved for RX
@@ -223,7 +222,7 @@ static inline u32 hecc_read_stamp(struct ti_hecc_priv *priv, u32 mbxno)
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}
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static inline void hecc_write_mbx (struct ti_hecc_priv * priv , u32 mbxno ,
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- u32 reg , u32 val )
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+ u32 reg , u32 val )
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{
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__raw_writel (val , priv -> mbx + mbxno * 0x10 + reg );
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}
@@ -244,13 +243,13 @@ static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg)
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}
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static inline void hecc_set_bit (struct ti_hecc_priv * priv , int reg ,
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- u32 bit_mask )
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+ u32 bit_mask )
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{
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hecc_write (priv , reg , hecc_read (priv , reg ) | bit_mask );
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}
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static inline void hecc_clear_bit (struct ti_hecc_priv * priv , int reg ,
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- u32 bit_mask )
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+ u32 bit_mask )
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{
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hecc_write (priv , reg , hecc_read (priv , reg ) & ~bit_mask );
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}
@@ -272,8 +271,8 @@ static int ti_hecc_set_btc(struct ti_hecc_priv *priv)
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if (bit_timing -> brp > 4 )
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can_btc |= HECC_CANBTC_SAM ;
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else
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- netdev_warn (priv -> ndev , "WARN: Triple"
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- " sampling not set due to h/w limitations" );
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+ netdev_warn (priv -> ndev ,
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+ "WARN: Triple sampling not set due to h/w limitations" );
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}
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can_btc |= ((bit_timing -> sjw - 1 ) & 0x3 ) << 8 ;
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can_btc |= ((bit_timing -> brp - 1 ) & 0xFF ) << 16 ;
@@ -309,8 +308,7 @@ static void ti_hecc_reset(struct net_device *ndev)
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/* Set change control request and wait till enabled */
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hecc_set_bit (priv , HECC_CANMC , HECC_CANMC_CCR );
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- /*
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- * INFO: It has been observed that at times CCE bit may not be
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+ /* INFO: It has been observed that at times CCE bit may not be
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* set and hw seems to be ok even if this bit is not set so
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* timing out with a timing of 1ms to respect the specs
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*/
@@ -320,8 +318,7 @@ static void ti_hecc_reset(struct net_device *ndev)
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udelay (10 );
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}
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- /*
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- * Note: On HECC, BTC can be programmed only in initialization mode, so
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+ /* Note: On HECC, BTC can be programmed only in initialization mode, so
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* it is expected that the can bittiming parameters are set via ip
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* utility before the device is opened
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*/
@@ -330,13 +327,11 @@ static void ti_hecc_reset(struct net_device *ndev)
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/* Clear CCR (and CANMC register) and wait for CCE = 0 enable */
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hecc_write (priv , HECC_CANMC , 0 );
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- /*
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- * INFO: CAN net stack handles bus off and hence disabling auto-bus-on
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+ /* INFO: CAN net stack handles bus off and hence disabling auto-bus-on
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* hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO);
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*/
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- /*
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- * INFO: It has been observed that at times CCE bit may not be
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+ /* INFO: It has been observed that at times CCE bit may not be
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* set and hw seems to be ok even if this bit is not set so
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*/
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cnt = HECC_CCE_WAIT_COUNT ;
@@ -369,7 +364,8 @@ static void ti_hecc_start(struct net_device *ndev)
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/* put HECC in initialization mode and set btc */
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ti_hecc_reset (ndev );
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- priv -> tx_head = priv -> tx_tail = HECC_TX_MASK ;
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+ priv -> tx_head = HECC_TX_MASK ;
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+ priv -> tx_tail = HECC_TX_MASK ;
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/* Enable local and global acceptance mask registers */
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hecc_write (priv , HECC_CANGAM , HECC_SET_REG );
@@ -395,7 +391,7 @@ static void ti_hecc_start(struct net_device *ndev)
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} else {
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hecc_write (priv , HECC_CANMIL , 0 );
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hecc_write (priv , HECC_CANGIM ,
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- HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN );
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+ HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN );
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}
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priv -> can .state = CAN_STATE_ERROR_ACTIVE ;
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}
@@ -429,7 +425,7 @@ static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode)
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}
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static int ti_hecc_get_berr_counter (const struct net_device * ndev ,
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- struct can_berr_counter * bec )
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+ struct can_berr_counter * bec )
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{
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struct ti_hecc_priv * priv = netdev_priv (ndev );
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@@ -439,8 +435,7 @@ static int ti_hecc_get_berr_counter(const struct net_device *ndev,
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return 0 ;
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}
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- /*
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- * ti_hecc_xmit: HECC Transmit
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+ /* ti_hecc_xmit: HECC Transmit
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*
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* The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the
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* priority of the mailbox for tranmission is dependent upon priority setting
@@ -478,8 +473,8 @@ static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev)
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spin_unlock_irqrestore (& priv -> mbx_lock , flags );
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netif_stop_queue (ndev );
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netdev_err (priv -> ndev ,
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- "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n" ,
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- priv -> tx_head , priv -> tx_tail );
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+ "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n" ,
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+ priv -> tx_head , priv -> tx_tail );
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return NETDEV_TX_BUSY ;
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}
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spin_unlock_irqrestore (& priv -> mbx_lock , flags );
@@ -496,18 +491,18 @@ static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev)
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data = (cf -> can_id & CAN_SFF_MASK ) << 18 ;
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hecc_write_mbx (priv , mbxno , HECC_CANMID , data );
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hecc_write_mbx (priv , mbxno , HECC_CANMDL ,
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- be32_to_cpu (* (__be32 * )(cf -> data )));
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+ be32_to_cpu (* (__be32 * )(cf -> data )));
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if (cf -> can_dlc > 4 )
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hecc_write_mbx (priv , mbxno , HECC_CANMDH ,
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- be32_to_cpu (* (__be32 * )(cf -> data + 4 )));
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+ be32_to_cpu (* (__be32 * )(cf -> data + 4 )));
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else
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* (u32 * )(cf -> data + 4 ) = 0 ;
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can_put_echo_skb (skb , ndev , mbxno );
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spin_lock_irqsave (& priv -> mbx_lock , flags );
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-- priv -> tx_head ;
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if ((hecc_read (priv , HECC_CANME ) & BIT (get_tx_head_mb (priv ))) ||
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- (priv -> tx_head & HECC_TX_MASK ) == HECC_TX_MASK ) {
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+ (priv -> tx_head & HECC_TX_MASK ) == HECC_TX_MASK ) {
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netif_stop_queue (ndev );
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}
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hecc_set_bit (priv , HECC_CANME , mbx_mask );
@@ -520,7 +515,8 @@ static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev)
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return NETDEV_TX_OK ;
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}
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- static inline struct ti_hecc_priv * rx_offload_to_priv (struct can_rx_offload * offload )
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+ static inline
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+ struct ti_hecc_priv * rx_offload_to_priv (struct can_rx_offload * offload )
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{
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return container_of (offload , struct ti_hecc_priv , offload );
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}
@@ -530,18 +526,19 @@ static unsigned int ti_hecc_mailbox_read(struct can_rx_offload *offload,
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u32 * timestamp , unsigned int mbxno )
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{
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struct ti_hecc_priv * priv = rx_offload_to_priv (offload );
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- u32 data , mbx_mask ;
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+ u32 data ;
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- mbx_mask = BIT (mbxno );
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data = hecc_read_mbx (priv , mbxno , HECC_CANMID );
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if (data & HECC_CANMID_IDE )
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cf -> can_id = (data & CAN_EFF_MASK ) | CAN_EFF_FLAG ;
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else
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cf -> can_id = (data >> 18 ) & CAN_SFF_MASK ;
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+
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data = hecc_read_mbx (priv , mbxno , HECC_CANMCF );
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if (data & HECC_CANMCF_RTR )
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cf -> can_id |= CAN_RTR_FLAG ;
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cf -> can_dlc = get_can_dlc (data & 0xF );
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+
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data = hecc_read_mbx (priv , mbxno , HECC_CANMDL );
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* (__be32 * )(cf -> data ) = cpu_to_be32 (data );
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if (cf -> can_dlc > 4 ) {
@@ -555,7 +552,7 @@ static unsigned int ti_hecc_mailbox_read(struct can_rx_offload *offload,
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}
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static int ti_hecc_error (struct net_device * ndev , int int_status ,
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- int err_status )
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+ int err_status )
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{
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struct ti_hecc_priv * priv = netdev_priv (ndev );
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struct can_frame * cf ;
@@ -567,7 +564,8 @@ static int ti_hecc_error(struct net_device *ndev, int int_status,
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if (!skb ) {
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if (printk_ratelimit ())
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netdev_err (priv -> ndev ,
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- "ti_hecc_error: alloc_can_err_skb() failed\n" );
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+ "%s: alloc_can_err_skb() failed\n" ,
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+ __func__ );
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return - ENOMEM ;
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}
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@@ -601,8 +599,7 @@ static int ti_hecc_error(struct net_device *ndev, int int_status,
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hecc_clear_bit (priv , HECC_CANMC , HECC_CANMC_CCR );
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}
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- /*
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- * Need to check busoff condition in error status register too to
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+ /* Need to check busoff condition in error status register too to
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* ensure warning interrupts don't hog the system
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*/
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if ((int_status & HECC_CANGIF_BOIF ) || (err_status & HECC_CANES_BO )) {
@@ -656,15 +653,16 @@ static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id)
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unsigned long flags , rx_pending ;
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int_status = hecc_read (priv ,
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- (priv -> use_hecc1int ) ? HECC_CANGIF1 : HECC_CANGIF0 );
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+ priv -> use_hecc1int ?
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+ HECC_CANGIF1 : HECC_CANGIF0 );
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if (!int_status )
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return IRQ_NONE ;
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err_status = hecc_read (priv , HECC_CANES );
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if (err_status & (HECC_BUS_ERROR | HECC_CANES_BO |
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- HECC_CANES_EP | HECC_CANES_EW ))
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- ti_hecc_error (ndev , int_status , err_status );
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+ HECC_CANES_EP | HECC_CANES_EW ))
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+ ti_hecc_error (ndev , int_status , err_status );
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if (int_status & HECC_CANGIF_GMIF ) {
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while (priv -> tx_tail - priv -> tx_head > 0 ) {
@@ -678,18 +676,19 @@ static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id)
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hecc_clear_bit (priv , HECC_CANME , mbx_mask );
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spin_unlock_irqrestore (& priv -> mbx_lock , flags );
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stamp = hecc_read_stamp (priv , mbxno );
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- stats -> tx_bytes += can_rx_offload_get_echo_skb (& priv -> offload ,
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- mbxno , stamp );
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+ stats -> tx_bytes +=
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+ can_rx_offload_get_echo_skb (& priv -> offload ,
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+ mbxno , stamp );
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stats -> tx_packets ++ ;
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can_led_event (ndev , CAN_LED_EVENT_TX );
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-- priv -> tx_tail ;
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}
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/* restart queue if wrap-up or if queue stalled on last pkt */
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- if ((( priv -> tx_head == priv -> tx_tail ) &&
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- ((priv -> tx_head & HECC_TX_MASK ) != HECC_TX_MASK )) ||
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- (((priv -> tx_tail & HECC_TX_MASK ) == HECC_TX_MASK ) &&
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- ((priv -> tx_head & HECC_TX_MASK ) == HECC_TX_MASK )))
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+ if ((priv -> tx_head == priv -> tx_tail &&
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+ ((priv -> tx_head & HECC_TX_MASK ) != HECC_TX_MASK )) ||
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+ (((priv -> tx_tail & HECC_TX_MASK ) == HECC_TX_MASK ) &&
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+ ((priv -> tx_head & HECC_TX_MASK ) == HECC_TX_MASK )))
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netif_wake_queue (ndev );
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/* offload RX mailboxes and let NAPI deliver them */
@@ -718,7 +717,7 @@ static int ti_hecc_open(struct net_device *ndev)
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int err ;
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err = request_irq (ndev -> irq , ti_hecc_interrupt , IRQF_SHARED ,
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- ndev -> name , ndev );
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+ ndev -> name , ndev );
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if (err ) {
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netdev_err (ndev , "error requesting interrupt\n" );
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return err ;
@@ -894,7 +893,7 @@ static int ti_hecc_probe(struct platform_device *pdev)
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devm_can_led_init (ndev );
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dev_info (& pdev -> dev , "device registered (reg_base=%p, irq=%u)\n" ,
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- priv -> base , (u32 ) ndev -> irq );
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+ priv -> base , (u32 )ndev -> irq );
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return 0 ;
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