|
48 | 48 | struct mlxsw_reg_info {
|
49 | 49 | u16 id;
|
50 | 50 | u16 len; /* In u8 */
|
| 51 | + const char *name; |
51 | 52 | };
|
52 | 53 |
|
53 | 54 | #define MLXSW_REG_DEFINE(_name, _id, _len) \
|
54 | 55 | static const struct mlxsw_reg_info mlxsw_reg_##_name = { \
|
55 | 56 | .id = _id, \
|
56 | 57 | .len = _len, \
|
| 58 | + .name = #_name, \ |
57 | 59 | }
|
58 | 60 |
|
59 | 61 | #define MLXSW_REG(type) (&mlxsw_reg_##type)
|
@@ -5082,132 +5084,80 @@ static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
|
5082 | 5084 | mlxsw_reg_sbib_buff_size_set(payload, buff_size);
|
5083 | 5085 | }
|
5084 | 5086 |
|
| 5087 | +static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { |
| 5088 | + MLXSW_REG(sgcr), |
| 5089 | + MLXSW_REG(spad), |
| 5090 | + MLXSW_REG(smid), |
| 5091 | + MLXSW_REG(sspr), |
| 5092 | + MLXSW_REG(sfdat), |
| 5093 | + MLXSW_REG(sfd), |
| 5094 | + MLXSW_REG(sfn), |
| 5095 | + MLXSW_REG(spms), |
| 5096 | + MLXSW_REG(spvid), |
| 5097 | + MLXSW_REG(spvm), |
| 5098 | + MLXSW_REG(spaft), |
| 5099 | + MLXSW_REG(sfgc), |
| 5100 | + MLXSW_REG(sftr), |
| 5101 | + MLXSW_REG(sfdf), |
| 5102 | + MLXSW_REG(sldr), |
| 5103 | + MLXSW_REG(slcr), |
| 5104 | + MLXSW_REG(slcor), |
| 5105 | + MLXSW_REG(spmlr), |
| 5106 | + MLXSW_REG(svfa), |
| 5107 | + MLXSW_REG(svpe), |
| 5108 | + MLXSW_REG(sfmr), |
| 5109 | + MLXSW_REG(spvmlr), |
| 5110 | + MLXSW_REG(qtct), |
| 5111 | + MLXSW_REG(qeec), |
| 5112 | + MLXSW_REG(pmlp), |
| 5113 | + MLXSW_REG(pmtu), |
| 5114 | + MLXSW_REG(ptys), |
| 5115 | + MLXSW_REG(ppad), |
| 5116 | + MLXSW_REG(paos), |
| 5117 | + MLXSW_REG(pfcc), |
| 5118 | + MLXSW_REG(ppcnt), |
| 5119 | + MLXSW_REG(pptb), |
| 5120 | + MLXSW_REG(pbmc), |
| 5121 | + MLXSW_REG(pspa), |
| 5122 | + MLXSW_REG(htgt), |
| 5123 | + MLXSW_REG(hpkt), |
| 5124 | + MLXSW_REG(rgcr), |
| 5125 | + MLXSW_REG(ritr), |
| 5126 | + MLXSW_REG(ratr), |
| 5127 | + MLXSW_REG(ralta), |
| 5128 | + MLXSW_REG(ralst), |
| 5129 | + MLXSW_REG(raltb), |
| 5130 | + MLXSW_REG(ralue), |
| 5131 | + MLXSW_REG(rauht), |
| 5132 | + MLXSW_REG(raleu), |
| 5133 | + MLXSW_REG(rauhtd), |
| 5134 | + MLXSW_REG(mfcr), |
| 5135 | + MLXSW_REG(mfsc), |
| 5136 | + MLXSW_REG(mfsm), |
| 5137 | + MLXSW_REG(mtcap), |
| 5138 | + MLXSW_REG(mtmp), |
| 5139 | + MLXSW_REG(mpat), |
| 5140 | + MLXSW_REG(mpar), |
| 5141 | + MLXSW_REG(mlcr), |
| 5142 | + MLXSW_REG(sbpr), |
| 5143 | + MLXSW_REG(sbcm), |
| 5144 | + MLXSW_REG(sbpm), |
| 5145 | + MLXSW_REG(sbmm), |
| 5146 | + MLXSW_REG(sbsr), |
| 5147 | + MLXSW_REG(sbib), |
| 5148 | +}; |
| 5149 | + |
5085 | 5150 | static inline const char *mlxsw_reg_id_str(u16 reg_id)
|
5086 | 5151 | {
|
5087 |
| - switch (reg_id) { |
5088 |
| - case MLXSW_REG_SGCR_ID: |
5089 |
| - return "SGCR"; |
5090 |
| - case MLXSW_REG_SPAD_ID: |
5091 |
| - return "SPAD"; |
5092 |
| - case MLXSW_REG_SMID_ID: |
5093 |
| - return "SMID"; |
5094 |
| - case MLXSW_REG_SSPR_ID: |
5095 |
| - return "SSPR"; |
5096 |
| - case MLXSW_REG_SFDAT_ID: |
5097 |
| - return "SFDAT"; |
5098 |
| - case MLXSW_REG_SFD_ID: |
5099 |
| - return "SFD"; |
5100 |
| - case MLXSW_REG_SFN_ID: |
5101 |
| - return "SFN"; |
5102 |
| - case MLXSW_REG_SPMS_ID: |
5103 |
| - return "SPMS"; |
5104 |
| - case MLXSW_REG_SPVID_ID: |
5105 |
| - return "SPVID"; |
5106 |
| - case MLXSW_REG_SPVM_ID: |
5107 |
| - return "SPVM"; |
5108 |
| - case MLXSW_REG_SPAFT_ID: |
5109 |
| - return "SPAFT"; |
5110 |
| - case MLXSW_REG_SFGC_ID: |
5111 |
| - return "SFGC"; |
5112 |
| - case MLXSW_REG_SFTR_ID: |
5113 |
| - return "SFTR"; |
5114 |
| - case MLXSW_REG_SFDF_ID: |
5115 |
| - return "SFDF"; |
5116 |
| - case MLXSW_REG_SLDR_ID: |
5117 |
| - return "SLDR"; |
5118 |
| - case MLXSW_REG_SLCR_ID: |
5119 |
| - return "SLCR"; |
5120 |
| - case MLXSW_REG_SLCOR_ID: |
5121 |
| - return "SLCOR"; |
5122 |
| - case MLXSW_REG_SPMLR_ID: |
5123 |
| - return "SPMLR"; |
5124 |
| - case MLXSW_REG_SVFA_ID: |
5125 |
| - return "SVFA"; |
5126 |
| - case MLXSW_REG_SVPE_ID: |
5127 |
| - return "SVPE"; |
5128 |
| - case MLXSW_REG_SFMR_ID: |
5129 |
| - return "SFMR"; |
5130 |
| - case MLXSW_REG_SPVMLR_ID: |
5131 |
| - return "SPVMLR"; |
5132 |
| - case MLXSW_REG_QTCT_ID: |
5133 |
| - return "QTCT"; |
5134 |
| - case MLXSW_REG_QEEC_ID: |
5135 |
| - return "QEEC"; |
5136 |
| - case MLXSW_REG_PMLP_ID: |
5137 |
| - return "PMLP"; |
5138 |
| - case MLXSW_REG_PMTU_ID: |
5139 |
| - return "PMTU"; |
5140 |
| - case MLXSW_REG_PTYS_ID: |
5141 |
| - return "PTYS"; |
5142 |
| - case MLXSW_REG_PPAD_ID: |
5143 |
| - return "PPAD"; |
5144 |
| - case MLXSW_REG_PAOS_ID: |
5145 |
| - return "PAOS"; |
5146 |
| - case MLXSW_REG_PFCC_ID: |
5147 |
| - return "PFCC"; |
5148 |
| - case MLXSW_REG_PPCNT_ID: |
5149 |
| - return "PPCNT"; |
5150 |
| - case MLXSW_REG_PPTB_ID: |
5151 |
| - return "PPTB"; |
5152 |
| - case MLXSW_REG_PBMC_ID: |
5153 |
| - return "PBMC"; |
5154 |
| - case MLXSW_REG_PSPA_ID: |
5155 |
| - return "PSPA"; |
5156 |
| - case MLXSW_REG_HTGT_ID: |
5157 |
| - return "HTGT"; |
5158 |
| - case MLXSW_REG_HPKT_ID: |
5159 |
| - return "HPKT"; |
5160 |
| - case MLXSW_REG_RGCR_ID: |
5161 |
| - return "RGCR"; |
5162 |
| - case MLXSW_REG_RITR_ID: |
5163 |
| - return "RITR"; |
5164 |
| - case MLXSW_REG_RATR_ID: |
5165 |
| - return "RATR"; |
5166 |
| - case MLXSW_REG_RALTA_ID: |
5167 |
| - return "RALTA"; |
5168 |
| - case MLXSW_REG_RALST_ID: |
5169 |
| - return "RALST"; |
5170 |
| - case MLXSW_REG_RALTB_ID: |
5171 |
| - return "RALTB"; |
5172 |
| - case MLXSW_REG_RALUE_ID: |
5173 |
| - return "RALUE"; |
5174 |
| - case MLXSW_REG_RAUHT_ID: |
5175 |
| - return "RAUHT"; |
5176 |
| - case MLXSW_REG_RALEU_ID: |
5177 |
| - return "RALEU"; |
5178 |
| - case MLXSW_REG_RAUHTD_ID: |
5179 |
| - return "RAUHTD"; |
5180 |
| - case MLXSW_REG_MFCR_ID: |
5181 |
| - return "MFCR"; |
5182 |
| - case MLXSW_REG_MFSC_ID: |
5183 |
| - return "MFSC"; |
5184 |
| - case MLXSW_REG_MFSM_ID: |
5185 |
| - return "MFSM"; |
5186 |
| - case MLXSW_REG_MTCAP_ID: |
5187 |
| - return "MTCAP"; |
5188 |
| - case MLXSW_REG_MPAT_ID: |
5189 |
| - return "MPAT"; |
5190 |
| - case MLXSW_REG_MPAR_ID: |
5191 |
| - return "MPAR"; |
5192 |
| - case MLXSW_REG_MTMP_ID: |
5193 |
| - return "MTMP"; |
5194 |
| - case MLXSW_REG_MLCR_ID: |
5195 |
| - return "MLCR"; |
5196 |
| - case MLXSW_REG_SBPR_ID: |
5197 |
| - return "SBPR"; |
5198 |
| - case MLXSW_REG_SBCM_ID: |
5199 |
| - return "SBCM"; |
5200 |
| - case MLXSW_REG_SBPM_ID: |
5201 |
| - return "SBPM"; |
5202 |
| - case MLXSW_REG_SBMM_ID: |
5203 |
| - return "SBMM"; |
5204 |
| - case MLXSW_REG_SBSR_ID: |
5205 |
| - return "SBSR"; |
5206 |
| - case MLXSW_REG_SBIB_ID: |
5207 |
| - return "SBIB"; |
5208 |
| - default: |
5209 |
| - return "*UNKNOWN*"; |
| 5152 | + const struct mlxsw_reg_info *reg_info; |
| 5153 | + int i; |
| 5154 | + |
| 5155 | + for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { |
| 5156 | + reg_info = mlxsw_reg_infos[i]; |
| 5157 | + if (reg_info->id == reg_id) |
| 5158 | + return reg_info->name; |
5210 | 5159 | }
|
| 5160 | + return "*UNKNOWN*"; |
5211 | 5161 | }
|
5212 | 5162 |
|
5213 | 5163 | /* PUDE - Port Up / Down Event
|
|
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