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jacob-kelleranguy11
jacob-keller
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anguy11
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ice: process 1588 PTP capabilities during initialization
The device firmware reports PTP clock capabilities to each PF during initialization. This includes various information for both the overall device and the individual function, including For functions: * whether this function has timesync enabled * whether this function owns one of the 2 possible clock timers, and which one * which timer the function is associated with * the clock frequency, if the device supports multiple clock frequencies * The GPIO pin association for the timer owned by this PF, if any For the device: * Which PF owns timer 0, if any * Which PF owns timer 1, if any * whether timer 0 is enabled * whether timer 1 is enabled Extract the bits from the capabilities information reported by firmware and store them in the device and function capability structures.o This information will be used in a future change to have the function driver enable PTP hardware clock support. Signed-off-by: Jacob Keller <[email protected]> Tested-by: Tony Brelinski <[email protected]> Signed-off-by: Tony Nguyen <[email protected]>
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‎drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -108,6 +108,7 @@ struct ice_aqc_list_caps_elem {
108108
#define ICE_AQC_CAPS_TXQS 0x0042
109109
#define ICE_AQC_CAPS_MSIX 0x0043
110110
#define ICE_AQC_CAPS_FD 0x0045
111+
#define ICE_AQC_CAPS_1588 0x0046
111112
#define ICE_AQC_CAPS_MAX_MTU 0x0047
112113
#define ICE_AQC_CAPS_NVM_VER 0x0048
113114
#define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049

‎drivers/net/ethernet/intel/ice/ice_common.c

Lines changed: 99 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2092,6 +2092,48 @@ ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
20922092
func_p->guar_num_vsi);
20932093
}
20942094

2095+
/**
2096+
* ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps
2097+
* @hw: pointer to the HW struct
2098+
* @func_p: pointer to function capabilities structure
2099+
* @cap: pointer to the capability element to parse
2100+
*
2101+
* Extract function capabilities for ICE_AQC_CAPS_1588.
2102+
*/
2103+
static void
2104+
ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2105+
struct ice_aqc_list_caps_elem *cap)
2106+
{
2107+
struct ice_ts_func_info *info = &func_p->ts_func_info;
2108+
u32 number = le32_to_cpu(cap->number);
2109+
2110+
info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0);
2111+
func_p->common_cap.ieee_1588 = info->ena;
2112+
2113+
info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0);
2114+
info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0);
2115+
info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0);
2116+
info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0);
2117+
2118+
info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S;
2119+
info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
2120+
2121+
ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n",
2122+
func_p->common_cap.ieee_1588);
2123+
ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n",
2124+
info->src_tmr_owned);
2125+
ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n",
2126+
info->tmr_ena);
2127+
ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n",
2128+
info->tmr_index_owned);
2129+
ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n",
2130+
info->tmr_index_assoc);
2131+
ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n",
2132+
info->clk_freq);
2133+
ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n",
2134+
info->clk_src);
2135+
}
2136+
20952137
/**
20962138
* ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
20972139
* @hw: pointer to the HW struct
@@ -2158,6 +2200,9 @@ ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
21582200
case ICE_AQC_CAPS_VSI:
21592201
ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
21602202
break;
2203+
case ICE_AQC_CAPS_1588:
2204+
ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]);
2205+
break;
21612206
case ICE_AQC_CAPS_FD:
21622207
ice_parse_fdir_func_caps(hw, func_p);
21632208
break;
@@ -2230,6 +2275,57 @@ ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
22302275
dev_p->num_vsi_allocd_to_host);
22312276
}
22322277

2278+
/**
2279+
* ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps
2280+
* @hw: pointer to the HW struct
2281+
* @dev_p: pointer to device capabilities structure
2282+
* @cap: capability element to parse
2283+
*
2284+
* Parse ICE_AQC_CAPS_1588 for device capabilities.
2285+
*/
2286+
static void
2287+
ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2288+
struct ice_aqc_list_caps_elem *cap)
2289+
{
2290+
struct ice_ts_dev_info *info = &dev_p->ts_dev_info;
2291+
u32 logical_id = le32_to_cpu(cap->logical_id);
2292+
u32 phys_id = le32_to_cpu(cap->phys_id);
2293+
u32 number = le32_to_cpu(cap->number);
2294+
2295+
info->ena = ((number & ICE_TS_DEV_ENA_M) != 0);
2296+
dev_p->common_cap.ieee_1588 = info->ena;
2297+
2298+
info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M;
2299+
info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0);
2300+
info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0);
2301+
2302+
info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S;
2303+
info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0);
2304+
info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0);
2305+
2306+
info->ena_ports = logical_id;
2307+
info->tmr_own_map = phys_id;
2308+
2309+
ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n",
2310+
dev_p->common_cap.ieee_1588);
2311+
ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n",
2312+
info->tmr0_owner);
2313+
ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n",
2314+
info->tmr0_owned);
2315+
ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n",
2316+
info->tmr0_ena);
2317+
ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n",
2318+
info->tmr1_owner);
2319+
ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n",
2320+
info->tmr1_owned);
2321+
ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n",
2322+
info->tmr1_ena);
2323+
ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n",
2324+
info->ena_ports);
2325+
ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n",
2326+
info->tmr_own_map);
2327+
}
2328+
22332329
/**
22342330
* ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
22352331
* @hw: pointer to the HW struct
@@ -2291,6 +2387,9 @@ ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
22912387
case ICE_AQC_CAPS_VSI:
22922388
ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
22932389
break;
2390+
case ICE_AQC_CAPS_1588:
2391+
ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]);
2392+
break;
22942393
case ICE_AQC_CAPS_FD:
22952394
ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
22962395
break;

‎drivers/net/ethernet/intel/ice/ice_type.h

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -265,6 +265,7 @@ struct ice_hw_common_caps {
265265
u8 rss_table_entry_width; /* RSS Entry width in bits */
266266

267267
u8 dcb;
268+
u8 ieee_1588;
268269
u8 rdma;
269270

270271
bool nvm_update_pending_nvm;
@@ -277,6 +278,54 @@ struct ice_hw_common_caps {
277278
#define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
278279
};
279280

281+
/* IEEE 1588 TIME_SYNC specific info */
282+
/* Function specific definitions */
283+
#define ICE_TS_FUNC_ENA_M BIT(0)
284+
#define ICE_TS_SRC_TMR_OWND_M BIT(1)
285+
#define ICE_TS_TMR_ENA_M BIT(2)
286+
#define ICE_TS_TMR_IDX_OWND_S 4
287+
#define ICE_TS_TMR_IDX_OWND_M BIT(4)
288+
#define ICE_TS_CLK_FREQ_S 16
289+
#define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S)
290+
#define ICE_TS_CLK_SRC_S 20
291+
#define ICE_TS_CLK_SRC_M BIT(20)
292+
#define ICE_TS_TMR_IDX_ASSOC_S 24
293+
#define ICE_TS_TMR_IDX_ASSOC_M BIT(24)
294+
295+
struct ice_ts_func_info {
296+
/* Function specific info */
297+
u32 clk_freq;
298+
u8 clk_src;
299+
u8 tmr_index_assoc;
300+
u8 ena;
301+
u8 tmr_index_owned;
302+
u8 src_tmr_owned;
303+
u8 tmr_ena;
304+
};
305+
306+
/* Device specific definitions */
307+
#define ICE_TS_TMR0_OWNR_M 0x7
308+
#define ICE_TS_TMR0_OWND_M BIT(3)
309+
#define ICE_TS_TMR1_OWNR_S 4
310+
#define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S)
311+
#define ICE_TS_TMR1_OWND_M BIT(7)
312+
#define ICE_TS_DEV_ENA_M BIT(24)
313+
#define ICE_TS_TMR0_ENA_M BIT(25)
314+
#define ICE_TS_TMR1_ENA_M BIT(26)
315+
316+
struct ice_ts_dev_info {
317+
/* Device specific info */
318+
u32 ena_ports;
319+
u32 tmr_own_map;
320+
u32 tmr0_owner;
321+
u32 tmr1_owner;
322+
u8 tmr0_owned;
323+
u8 tmr1_owned;
324+
u8 ena;
325+
u8 tmr0_ena;
326+
u8 tmr1_ena;
327+
};
328+
280329
/* Function specific capabilities */
281330
struct ice_hw_func_caps {
282331
struct ice_hw_common_caps common_cap;
@@ -285,6 +334,7 @@ struct ice_hw_func_caps {
285334
u32 guar_num_vsi;
286335
u32 fd_fltr_guar; /* Number of filters guaranteed */
287336
u32 fd_fltr_best_effort; /* Number of best effort filters */
337+
struct ice_ts_func_info ts_func_info;
288338
};
289339

290340
/* Device wide capabilities */
@@ -293,6 +343,7 @@ struct ice_hw_dev_caps {
293343
u32 num_vfs_exposed; /* Total number of VFs exposed */
294344
u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
295345
u32 num_flow_director_fltr; /* Number of FD filters available */
346+
struct ice_ts_dev_info ts_dev_info;
296347
u32 num_funcs;
297348
};
298349

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