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RISC-V: hwprobe: Expose Zicboz extension and its block size
Expose Zicboz through hwprobe and also provide a key to extract its respective block size. Opportunistically add a macro and apply it to current extensions in order to avoid duplicating code. Signed-off-by: Andrew Jones <[email protected]> Reviewed-by: Evan Green <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
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Documentation/riscv/hwprobe.rst

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@@ -77,6 +77,9 @@ The following keys are defined:
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* :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined
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in version 1.0 of the Bit-Manipulation ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as
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ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
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* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
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information about the selected set of processors.
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@@ -96,3 +99,6 @@ The following keys are defined:
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* :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are
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not supported at all and will generate a misaligned address fault.
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* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
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represents the size of the Zicboz block in bytes.

arch/riscv/include/asm/hwprobe.h

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@@ -8,6 +8,6 @@
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#include <uapi/asm/hwprobe.h>
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#define RISCV_HWPROBE_MAX_KEY 5
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#define RISCV_HWPROBE_MAX_KEY 6
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#endif

arch/riscv/include/uapi/asm/hwprobe.h

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@@ -29,13 +29,15 @@ struct riscv_hwprobe {
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#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
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#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
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#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
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#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6)
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#define RISCV_HWPROBE_KEY_CPUPERF_0 5
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#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
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#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
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#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0)
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#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0)
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#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
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#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
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#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
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/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
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#endif

arch/riscv/kernel/sys_riscv.c

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@@ -145,26 +145,38 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
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for_each_cpu(cpu, cpus) {
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struct riscv_isainfo *isainfo = &hart_isa[cpu];
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if (riscv_isa_extension_available(isainfo->isa, ZBA))
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pair->value |= RISCV_HWPROBE_EXT_ZBA;
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else
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missing |= RISCV_HWPROBE_EXT_ZBA;
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if (riscv_isa_extension_available(isainfo->isa, ZBB))
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pair->value |= RISCV_HWPROBE_EXT_ZBB;
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else
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missing |= RISCV_HWPROBE_EXT_ZBB;
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if (riscv_isa_extension_available(isainfo->isa, ZBS))
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pair->value |= RISCV_HWPROBE_EXT_ZBS;
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else
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missing |= RISCV_HWPROBE_EXT_ZBS;
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#define EXT_KEY(ext) \
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do { \
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if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_EXT_##ext)) \
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pair->value |= RISCV_HWPROBE_EXT_##ext; \
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else \
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missing |= RISCV_HWPROBE_EXT_##ext; \
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} while (false)
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/*
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* Only use EXT_KEY() for extensions which can be exposed to userspace,
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* regardless of the kernel's configuration, as no other checks, besides
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* presence in the hart_isa bitmap, are made.
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*/
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EXT_KEY(ZBA);
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EXT_KEY(ZBB);
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EXT_KEY(ZBS);
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EXT_KEY(ZICBOZ);
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#undef EXT_KEY
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}
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/* Now turn off reporting features if any CPU is missing it. */
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pair->value &= ~missing;
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}
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static bool hwprobe_ext0_has(const struct cpumask *cpus, unsigned long ext)
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{
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struct riscv_hwprobe pair;
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hwprobe_isa_ext0(&pair, cpus);
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return (pair.value & ext);
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}
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static u64 hwprobe_misaligned(const struct cpumask *cpus)
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{
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int cpu;
@@ -215,6 +227,12 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
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pair->value = hwprobe_misaligned(cpus);
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break;
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case RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE:
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pair->value = 0;
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if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ))
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pair->value = riscv_cboz_block_size;
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break;
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/*
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* For forward compatibility, unknown keys don't fail the whole
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* call, but get their element key set to -1 and value set to 0

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