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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Arnd Bergmann: "Device-tree updates for arm64 platforms. For the first time I can remember, this is actually larger than the corresponding branch for 32-bit platforms overall, though that has more individual changes. A significant portion this time is due to added machine support: - Initial support for the Realtek RTD1295 SoC, along with the Zidoo X9S set-top-box - Initial support for Actions Semi S900 and the Bubblegum-96 single-board-cёmputer. - Rockchips support for the rk3399-Firefly single-board-computer gets added, this one stands out for being relatively fast, affordable and well₋supported, compared to many boards that only fall into one or two of the above categories. - Mediatek gains support for the mt6797 mobile-phone SoC platform and corresponding evaluation board. - Amlogic board support gets added for the NanoPi K2 and S905x LibreTech CC single-board computers and the R-Box Pro set-top-box - Allwinner board support gets added for the OrangePi Win, Orangepi Zero Plus 2, NanoPi NEO2 and Orange Pi Prime single board computers and the SoPine system-on-module. - Renesas board support for Salvator-XS and H3ULCB automotive development systems. - Socionext Uniphier board support for LD11-global and LD20-global, whatever those may be. - Broadcom adds support for the new Stingray communication processor in its iProc family, along with two reference boards. Other updates include: - For the hisicon platform, support for Hi3660-Hikey960 gets extended significantly. - Lots of smaller updates for Renesas, Amlogic, Rockchip, UniPhier, Broadcom, Allwinner, Hisilicon, Qualcomm, Marvell, and NXP" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (243 commits) ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers Revert "arm64: dts: marvell: add dma-mask in crypto nodes for 7k/8k" arm64: dts: mediatek: don't include missing file ARM64: dts: meson-gxl: Add Libre Technology CC support dt-bindings: arm: amlogic: Add Libre Technology CC board dt-bindings: add Libre Technology vendor prefix arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K arm64: dts: zte: Use - instead of @ for DT OPP entries arm64: dts: marvell: add gpio support for Armada 7K/8K arm64: dts: marvell: add pinctrl support for Armada 7K/8K arm64: dts: marvell: use new binding for the system controller on cp110 arm64: dts: marvell: remove *-clock-output-names on cp110 arm64: dts: marvell: use new bindings for xor clocks on ap806 arm64: dts: marvell: mcbin: enable the mdio node arm64: dts: Add Actions Semi S900 and Bubblegum-96 dt-bindings: Add vendor prefix for uCRobotics arm64: dts: marvell: add xmdio nodes for 7k/8k arm64: dts: marvell: add a comment on the cp110 slave node status arm64: dts: marvell: remove cpm crypto nodes from dts files arm64: dts: marvell: cp110: enable the crypto engine at the SoC level ...
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‎Documentation/devicetree/bindings/arm/amlogic.txt

Lines changed: 16 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -29,26 +29,35 @@ Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
2929
Required root node property:
3030
compatible: "amlogic,s912", "amlogic,meson-gxm";
3131

32-
Board compatible values:
32+
Board compatible values (alphabetically, grouped by SoC):
33+
3334
- "geniatech,atv1200" (Meson6)
35+
3436
- "minix,neo-x8" (Meson8)
35-
- "tronfy,mxq" (Meson8b)
37+
3638
- "hardkernel,odroid-c1" (Meson8b)
39+
- "tronfy,mxq" (Meson8b)
40+
41+
- "amlogic,p200" (Meson gxbb)
42+
- "amlogic,p201" (Meson gxbb)
43+
- "friendlyarm,nanopi-k2" (Meson gxbb)
44+
- "hardkernel,odroid-c2" (Meson gxbb)
45+
- "nexbox,a95x" (Meson gxbb or Meson gxl s905x)
3746
- "tronsmart,vega-s95-pro", "tronsmart,vega-s95" (Meson gxbb)
3847
- "tronsmart,vega-s95-meta", "tronsmart,vega-s95" (Meson gxbb)
3948
- "tronsmart,vega-s95-telos", "tronsmart,vega-s95" (Meson gxbb)
40-
- "hardkernel,odroid-c2" (Meson gxbb)
41-
- "amlogic,p200" (Meson gxbb)
42-
- "amlogic,p201" (Meson gxbb)
4349
- "wetek,hub" (Meson gxbb)
4450
- "wetek,play2" (Meson gxbb)
51+
4552
- "amlogic,p212" (Meson gxl s905x)
53+
- "hwacom,amazetv" (Meson gxl s905x)
4654
- "khadas,vim" (Meson gxl s905x)
55+
- "libretech,cc" (Meson gxl s905x)
4756

4857
- "amlogic,p230" (Meson gxl s905d)
4958
- "amlogic,p231" (Meson gxl s905d)
50-
- "hwacom,amazetv" (Meson gxl s905x)
59+
5160
- "amlogic,q200" (Meson gxm s912)
5261
- "amlogic,q201" (Meson gxm s912)
53-
- "nexbox,a95x" (Meson gxbb or Meson gxl s905x)
62+
- "kingnovel,r-box-pro" (Meson gxm S912)
5463
- "nexbox,a1" (Meson gxm s912)

‎Documentation/devicetree/bindings/arm/bcm/brcm,stingray.txt

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
Broadcom Stingray device tree bindings
2+
------------------------------------------------
3+
4+
Boards with Stingray shall have the following properties:
5+
6+
Required root node property:
7+
8+
Stingray Combo SVK board
9+
compatible = "brcm,bcm958742k", "brcm,stingray";
10+
11+
Stingray SST100 board
12+
compatible = "brcm,bcm958742t", "brcm,stingray";

‎Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,10 @@ Hi3660 SoC
44
Required root node properties:
55
- compatible = "hisilicon,hi3660";
66

7+
HiKey960 Board
8+
Required root node properties:
9+
- compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
10+
711
Hi3798cv200 SoC
812
Required root node properties:
913
- compatible = "hisilicon,hi3798cv200";

‎Documentation/devicetree/bindings/arm/mediatek.txt

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,8 @@ compatible: Must contain one of
1212
"mediatek,mt6592"
1313
"mediatek,mt6755"
1414
"mediatek,mt6795"
15+
"mediatek,mt6797"
16+
"mediatek,mt7622"
1517
"mediatek,mt7623"
1618
"mediatek,mt8127"
1719
"mediatek,mt8135"
@@ -38,6 +40,12 @@ Supported boards:
3840
- Evaluation board for MT6795(Helio X10):
3941
Required root node properties:
4042
- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
43+
- Evaluation board for MT6797(Helio X20):
44+
Required root node properties:
45+
- compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
46+
- Reference board variant 1 for MT7622:
47+
Required root node properties:
48+
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
4149
- Evaluation board for MT7623:
4250
Required root node properties:
4351
- compatible = "mediatek,mt7623-evb", "mediatek,mt7623";

‎Documentation/devicetree/bindings/arm/realtek.txt

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
Realtek platforms device tree bindings
2+
--------------------------------------
3+
4+
5+
RTD1295 SoC
6+
===========
7+
8+
Required root node properties:
9+
10+
- compatible : must contain "realtek,rtd1295"
11+
12+
13+
Root node property compatible must contain, depending on board:
14+
15+
- Zidoo X9S: "zidoo,x9s"
16+
17+
18+
Example:
19+
20+
compatible = "zidoo,x9s", "realtek,rtd1295";

‎Documentation/devicetree/bindings/arm/rockchip.txt

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,10 @@ Rockchip platforms device tree bindings
4242
Required root node properties:
4343
- compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288";
4444

45+
- Firefly Firefly-RK3399 board:
46+
Required root node properties:
47+
- compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
48+
4549
- ChipSPARK PopMetal-RK3288 board:
4650
Required root node properties:
4751
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";

‎Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller
33
Required properties:
44
- reg: Physical base address and size of the controller's register area.
55
- compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
6-
chip could be ls1021a, ls1043a, ls1046a, ls2080a etc.
6+
chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a etc.
77
- clocks: Input clock specifier. Refer to common clock bindings.
88
- interrupts: Interrupt specifier. Refer to interrupt binding.
99

‎Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt

Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -219,3 +219,79 @@ BCM63138
219219
--------
220220
PLL and leaf clock compatible strings for BCM63138 are:
221221
"brcm,bcm63138-armpll"
222+
223+
Stingray
224+
-----------
225+
PLL and leaf clock compatible strings for Stingray are:
226+
"brcm,sr-genpll0"
227+
"brcm,sr-genpll1"
228+
"brcm,sr-genpll2"
229+
"brcm,sr-genpll3"
230+
"brcm,sr-genpll4"
231+
"brcm,sr-genpll5"
232+
"brcm,sr-genpll6"
233+
234+
"brcm,sr-lcpll0"
235+
"brcm,sr-lcpll1"
236+
"brcm,sr-lcpll-pcie"
237+
238+
239+
The following table defines the set of PLL/clock index and ID for Stingray.
240+
These clock IDs are defined in:
241+
"include/dt-bindings/clock/bcm-sr.h"
242+
243+
Clock Source Index ID
244+
--- ----- ----- ---------
245+
crystal N/A N/A N/A
246+
crmu_ref25m crystal N/A N/A
247+
248+
genpll0 crystal 0 BCM_SR_GENPLL0
249+
clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
250+
clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
251+
clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
252+
clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
253+
clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
254+
clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
255+
256+
genpll1 crystal 0 BCM_SR_GENPLL1
257+
clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
258+
clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
259+
260+
genpll2 crystal 0 BCM_SR_GENPLL2
261+
clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
262+
clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
263+
clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
264+
clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
265+
clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH
266+
267+
genpll3 crystal 0 BCM_SR_GENPLL3
268+
clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
269+
clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
270+
271+
genpll4 crystal 0 BCM_SR_GENPLL4
272+
ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
273+
clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
274+
noc_clk genpll4 3 BCM_SR_GENPLL4_NOC_CLK
275+
clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
276+
clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
277+
278+
279+
genpll5 crystal 0 BCM_SR_GENPLL5
280+
fs4_hf_clk genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
281+
crypto_ae_clk genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
282+
raid_ae_clk genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
283+
284+
genpll6 crystal 0 BCM_SR_GENPLL6
285+
48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
286+
287+
lcpll0 crystal 0 BCM_SR_LCPLL0
288+
clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
289+
clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
290+
clk_usb_ref lcpll0 3 BCM_SR_LCPLL0_USB_REF_CLK
291+
sata_refpn lcpll0 3 BCM_SR_LCPLL0_SATA_REFPN_CLK
292+
293+
lcpll1 crystal 0 BCM_SR_LCPLL1
294+
wan lcpll1 1 BCM_SR_LCPLL0_WAN_CLK
295+
296+
lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
297+
pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK

‎Documentation/devicetree/bindings/i2c/i2c-mt6577.txt renamed to ‎Documentation/devicetree/bindings/i2c/i2c-mtk.txt

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4,11 +4,11 @@ The Mediatek's I2C controller is used to interface with I2C devices.
44

55
Required properties:
66
- compatible: value should be either of the following.
7-
(a) "mediatek,mt6577-i2c", for i2c compatible with mt6577 i2c.
8-
(b) "mediatek,mt6589-i2c", for i2c compatible with mt6589 i2c.
9-
(c) "mediatek,mt8127-i2c", for i2c compatible with mt8127 i2c.
10-
(d) "mediatek,mt8135-i2c", for i2c compatible with mt8135 i2c.
11-
(e) "mediatek,mt8173-i2c", for i2c compatible with mt8173 i2c.
7+
"mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for Mediatek mt2701
8+
"mediatek,mt6577-i2c": for i2c compatible with mt6577.
9+
"mediatek,mt6589-i2c": for i2c compatible with mt6589.
10+
"mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for i2c compatible with mt7623.
11+
"mediatek,mt8173-i2c": for i2c compatible with mt8173.
1212
- reg: physical base address of the controller and dma base, length of memory
1313
mapped region.
1414
- interrupts: interrupt number to the cpu.

‎Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt

Lines changed: 15 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,21 +1,23 @@
1-
+Mediatek 65xx/67xx/81xx sysirq
1+
+Mediatek MT65xx/MT67xx/MT81xx sysirq
22

33
Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
44
interrupt.
55

66
Required properties:
7-
- compatible: should be one of:
8-
"mediatek,mt8173-sysirq"
9-
"mediatek,mt8135-sysirq"
10-
"mediatek,mt8127-sysirq"
11-
"mediatek,mt6795-sysirq"
12-
"mediatek,mt6755-sysirq"
13-
"mediatek,mt6592-sysirq"
14-
"mediatek,mt6589-sysirq"
15-
"mediatek,mt6582-sysirq"
16-
"mediatek,mt6580-sysirq"
17-
"mediatek,mt6577-sysirq"
18-
"mediatek,mt2701-sysirq"
7+
- compatible: should be
8+
"mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
9+
"mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
10+
"mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
11+
"mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
12+
"mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
13+
"mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
14+
"mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755
15+
"mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592
16+
"mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589
17+
"mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
18+
"mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
19+
"mediatek,mt6577-sysirq": for MT6577
20+
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
1921
- interrupt-controller : Identifies the node as an interrupt controller
2022
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
2123
- interrupt-parent: phandle of irq parent for sysirq. The parent must

‎Documentation/devicetree/bindings/mfd/hi6421.txt

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,9 @@
11
* HI6421 Multi-Functional Device (MFD), by HiSilicon Ltd.
22

33
Required parent device properties:
4-
- compatible : contains "hisilicon,hi6421-pmic";
4+
- compatible : One of the following chip-specific strings:
5+
"hisilicon,hi6421-pmic";
6+
"hisilicon,hi6421v530-pmic";
57
- reg : register range space of hi6421;
68

79
Supported Hi6421 sub-devices include:

‎Documentation/devicetree/bindings/mmc/fsl-esdhc.txt

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,20 @@ This file documents differences between the core properties described
77
by mmc.txt and the properties used by the sdhci-esdhc driver.
88

99
Required properties:
10+
- compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
11+
Possible compatibles for PowerPC:
12+
"fsl,mpc8536-esdhc"
13+
"fsl,mpc8378-esdhc"
14+
"fsl,p2020-esdhc"
15+
"fsl,p4080-esdhc"
16+
"fsl,t1040-esdhc"
17+
"fsl,t4240-esdhc"
18+
Possible compatibles for ARM:
19+
"fsl,ls1012a-esdhc"
20+
"fsl,ls1088a-esdhc"
21+
"fsl,ls1043a-esdhc"
22+
"fsl,ls1046a-esdhc"
23+
"fsl,ls2080a-esdhc"
1024
- interrupt-parent : interrupt source phandle.
1125
- clock-frequency : specifies eSDHC base clock frequency.
1226

‎Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ extensions to the Synopsys Designware Mobile Storage Host Controller.
1212
Required Properties:
1313

1414
* compatible: should be one of the following.
15+
- "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
1516
- "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
1617
- "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
1718

‎Documentation/devicetree/bindings/pci/kirin-pcie.txt

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,50 @@
1+
HiSilicon Kirin SoCs PCIe host DT description
2+
3+
Kirin PCIe host controller is based on Designware PCI core.
4+
It shares common functions with PCIe Designware core driver
5+
and inherits common properties defined in
6+
Documentation/devicetree/bindings/pci/designware-pci.txt.
7+
8+
Additional properties are described here:
9+
10+
Required properties
11+
- compatible:
12+
"hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
13+
- reg: Should contain rc_dbi, apb, phy, config registers location and length.
14+
- reg-names: Must include the following entries:
15+
"dbi": controller configuration registers;
16+
"apb": apb Ctrl register defined by Kirin;
17+
"phy": apb PHY register defined by Kirin;
18+
"config": PCIe configuration space registers.
19+
- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
20+
21+
Optional properties:
22+
23+
Example based on kirin960:
24+
25+
pcie@f4000000 {
26+
compatible = "hisilicon,kirin-pcie";
27+
reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
28+
<0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
29+
reg-names = "dbi","apb","phy", "config";
30+
bus-range = <0x0 0x1>;
31+
#address-cells = <3>;
32+
#size-cells = <2>;
33+
device_type = "pci";
34+
ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
35+
num-lanes = <1>;
36+
#interrupt-cells = <1>;
37+
interrupt-map-mask = <0xf800 0 0 7>;
38+
interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
39+
<0x0 0 0 2 &gic 0 0 0 283 4>,
40+
<0x0 0 0 3 &gic 0 0 0 284 4>,
41+
<0x0 0 0 4 &gic 0 0 0 285 4>;
42+
clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
43+
<&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
44+
<&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
45+
<&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
46+
<&crg_ctrl HI3660_ACLK_GATE_PCIE>;
47+
clock-names = "pcie_phy_ref", "pcie_aux",
48+
"pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
49+
reset-gpios = <&gpio11 1 0 >;
50+
};

‎Documentation/devicetree/bindings/serial/mtk-uart.txt

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Original file line numberDiff line numberDiff line change
@@ -8,6 +8,8 @@ Required properties:
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* "mediatek,mt6589-uart" for MT6589 compatible UARTS
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* "mediatek,mt6755-uart" for MT6755 compatible UARTS
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* "mediatek,mt6795-uart" for MT6795 compatible UARTS
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* "mediatek,mt6797-uart" for MT6797 compatible UARTS
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* "mediatek,mt7622-uart" for MT7622 compatible UARTS
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* "mediatek,mt7623-uart" for MT7623 compatible UARTS
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* "mediatek,mt8127-uart" for MT8127 compatible UARTS
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* "mediatek,mt8135-uart" for MT8135 compatible UARTS

‎Documentation/devicetree/bindings/soc/mediatek/scpsys.txt

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,11 +9,14 @@ domain control.
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The driver implements the Generic PM domain bindings described in
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power/power_domain.txt. It provides the power domains defined in
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include/dt-bindings/power/mt8173-power.h and mt2701-power.h.
12+
- include/dt-bindings/power/mt8173-power.h
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- include/dt-bindings/power/mt6797-power.h
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- include/dt-bindings/power/mt2701-power.h
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Required properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-scpsys"
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- "mediatek,mt6797-scpsys"
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- "mediatek,mt8173-scpsys"
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- #power-domain-cells: Must be 1
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- reg: Address range of the SCPSYS unit
@@ -22,6 +25,7 @@ Required properties:
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These are clocks which hardware needs to be
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enabled before enabling certain power domains.
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Required clocks for MT2701: "mm", "mfg", "ethif"
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Required clocks for MT6797: "mm", "mfg", "vdec"
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Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
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Optional properties:

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