@@ -44,6 +44,7 @@ struct a6xx_gpu_state {
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struct msm_gpu_state_bo * gmu_log ;
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struct msm_gpu_state_bo * gmu_hfi ;
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+ struct msm_gpu_state_bo * gmu_debug ;
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s32 hfi_queue_history [2 ][HFI_HISTORY_SZ ];
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@@ -983,6 +984,7 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
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a6xx_state -> gmu_log = a6xx_snapshot_gmu_bo (a6xx_state , & a6xx_gpu -> gmu .log );
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a6xx_state -> gmu_hfi = a6xx_snapshot_gmu_bo (a6xx_state , & a6xx_gpu -> gmu .hfi );
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+ a6xx_state -> gmu_debug = a6xx_snapshot_gmu_bo (a6xx_state , & a6xx_gpu -> gmu .debug );
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a6xx_snapshot_gmu_hfi_history (gpu , a6xx_state );
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@@ -1274,6 +1276,16 @@ void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
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& gmu_hfi -> encoded );
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}
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+ drm_puts (p , "gmu-debug:\n" );
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+ if (a6xx_state -> gmu_debug ) {
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+ struct msm_gpu_state_bo * gmu_debug = a6xx_state -> gmu_debug ;
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+
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+ drm_printf (p , " iova: 0x%016llx\n" , gmu_debug -> iova );
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+ drm_printf (p , " size: %zu\n" , gmu_debug -> size );
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+ adreno_show_object (p , & gmu_debug -> data , gmu_debug -> size ,
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+ & gmu_debug -> encoded );
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+ }
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+
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drm_puts (p , "registers:\n" );
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for (i = 0 ; i < a6xx_state -> nr_registers ; i ++ ) {
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struct a6xx_gpu_state_obj * obj = & a6xx_state -> registers [i ];
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