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hayesorzFrancois Romieu
hayesorz
authored and
Francois Romieu
committed
r8169: support new chips of RTL8111F
Support new chips of RTL8111F. Signed-off-by: Hayes Wang <[email protected]>
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  • drivers/net/ethernet/realtek

1 file changed

+178
-2
lines changed

‎drivers/net/ethernet/realtek/r8169.c

Lines changed: 178 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,8 @@
4242
#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
4343
#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
4444
#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45+
#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46+
#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
4547
#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
4648

4749
#ifdef RTL8169_DEBUG
@@ -133,6 +135,8 @@ enum mac_version {
133135
RTL_GIGA_MAC_VER_32,
134136
RTL_GIGA_MAC_VER_33,
135137
RTL_GIGA_MAC_VER_34,
138+
RTL_GIGA_MAC_VER_35,
139+
RTL_GIGA_MAC_VER_36,
136140
RTL_GIGA_MAC_NONE = 0xff,
137141
};
138142

@@ -218,7 +222,11 @@ static const struct {
218222
[RTL_GIGA_MAC_VER_33] =
219223
_R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2),
220224
[RTL_GIGA_MAC_VER_34] =
221-
_R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3)
225+
_R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3),
226+
[RTL_GIGA_MAC_VER_35] =
227+
_R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1),
228+
[RTL_GIGA_MAC_VER_36] =
229+
_R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2)
222230
};
223231
#undef _R
224232

@@ -715,6 +723,8 @@ MODULE_FIRMWARE(FIRMWARE_8168E_1);
715723
MODULE_FIRMWARE(FIRMWARE_8168E_2);
716724
MODULE_FIRMWARE(FIRMWARE_8168E_3);
717725
MODULE_FIRMWARE(FIRMWARE_8105E_1);
726+
MODULE_FIRMWARE(FIRMWARE_8168F_1);
727+
MODULE_FIRMWARE(FIRMWARE_8168F_2);
718728

719729
static int rtl8169_open(struct net_device *dev);
720730
static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
@@ -1203,6 +1213,19 @@ static void rtl_link_chg_patch(struct rtl8169_private *tp)
12031213
ERIAR_EXGMAC);
12041214
rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
12051215
ERIAR_EXGMAC);
1216+
} else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1217+
tp->mac_version == RTL_GIGA_MAC_VER_36) {
1218+
if (RTL_R8(PHYstatus) & _1000bpsF) {
1219+
rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1220+
0x00000011, ERIAR_EXGMAC);
1221+
rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1222+
0x00000005, ERIAR_EXGMAC);
1223+
} else {
1224+
rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1225+
0x0000001f, ERIAR_EXGMAC);
1226+
rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1227+
0x0000003f, ERIAR_EXGMAC);
1228+
}
12061229
}
12071230
}
12081231

@@ -1742,6 +1765,10 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
17421765
u32 val;
17431766
int mac_version;
17441767
} mac_info[] = {
1768+
/* 8168F family. */
1769+
{ 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1770+
{ 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1771+
17451772
/* 8168E family. */
17461773
{ 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
17471774
{ 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
@@ -2876,6 +2903,97 @@ static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
28762903
rtl_writephy(tp, 0x1f, 0x0000);
28772904
}
28782905

2906+
static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
2907+
{
2908+
static const struct phy_reg phy_reg_init[] = {
2909+
/* Channel estimation fine tune */
2910+
{ 0x1f, 0x0003 },
2911+
{ 0x09, 0xa20f },
2912+
{ 0x1f, 0x0000 },
2913+
2914+
/* Modify green table for giga & fnet */
2915+
{ 0x1f, 0x0005 },
2916+
{ 0x05, 0x8b55 },
2917+
{ 0x06, 0x0000 },
2918+
{ 0x05, 0x8b5e },
2919+
{ 0x06, 0x0000 },
2920+
{ 0x05, 0x8b67 },
2921+
{ 0x06, 0x0000 },
2922+
{ 0x05, 0x8b70 },
2923+
{ 0x06, 0x0000 },
2924+
{ 0x1f, 0x0000 },
2925+
{ 0x1f, 0x0007 },
2926+
{ 0x1e, 0x0078 },
2927+
{ 0x17, 0x0000 },
2928+
{ 0x19, 0x00fb },
2929+
{ 0x1f, 0x0000 },
2930+
2931+
/* Modify green table for 10M */
2932+
{ 0x1f, 0x0005 },
2933+
{ 0x05, 0x8b79 },
2934+
{ 0x06, 0xaa00 },
2935+
{ 0x1f, 0x0000 },
2936+
2937+
/* Disable hiimpedance detection (RTCT) */
2938+
{ 0x1f, 0x0003 },
2939+
{ 0x01, 0x328a },
2940+
{ 0x1f, 0x0000 }
2941+
};
2942+
2943+
rtl_apply_firmware(tp);
2944+
2945+
rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2946+
2947+
/* For 4-corner performance improve */
2948+
rtl_writephy(tp, 0x1f, 0x0005);
2949+
rtl_writephy(tp, 0x05, 0x8b80);
2950+
rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
2951+
rtl_writephy(tp, 0x1f, 0x0000);
2952+
2953+
/* PHY auto speed down */
2954+
rtl_writephy(tp, 0x1f, 0x0007);
2955+
rtl_writephy(tp, 0x1e, 0x002d);
2956+
rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2957+
rtl_writephy(tp, 0x1f, 0x0000);
2958+
rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2959+
2960+
/* Improve 10M EEE waveform */
2961+
rtl_writephy(tp, 0x1f, 0x0005);
2962+
rtl_writephy(tp, 0x05, 0x8b86);
2963+
rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2964+
rtl_writephy(tp, 0x1f, 0x0000);
2965+
2966+
/* Improve 2-pair detection performance */
2967+
rtl_writephy(tp, 0x1f, 0x0005);
2968+
rtl_writephy(tp, 0x05, 0x8b85);
2969+
rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2970+
rtl_writephy(tp, 0x1f, 0x0000);
2971+
}
2972+
2973+
static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
2974+
{
2975+
rtl_apply_firmware(tp);
2976+
2977+
/* For 4-corner performance improve */
2978+
rtl_writephy(tp, 0x1f, 0x0005);
2979+
rtl_writephy(tp, 0x05, 0x8b80);
2980+
rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
2981+
rtl_writephy(tp, 0x1f, 0x0000);
2982+
2983+
/* PHY auto speed down */
2984+
rtl_writephy(tp, 0x1f, 0x0007);
2985+
rtl_writephy(tp, 0x1e, 0x002d);
2986+
rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2987+
rtl_writephy(tp, 0x1f, 0x0000);
2988+
rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2989+
2990+
/* Improve 10M EEE waveform */
2991+
rtl_writephy(tp, 0x1f, 0x0005);
2992+
rtl_writephy(tp, 0x05, 0x8b86);
2993+
rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2994+
rtl_writephy(tp, 0x1f, 0x0000);
2995+
}
2996+
28792997
static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
28802998
{
28812999
static const struct phy_reg phy_reg_init[] = {
@@ -3000,6 +3118,12 @@ static void rtl_hw_phy_config(struct net_device *dev)
30003118
case RTL_GIGA_MAC_VER_34:
30013119
rtl8168e_2_hw_phy_config(tp);
30023120
break;
3121+
case RTL_GIGA_MAC_VER_35:
3122+
rtl8168f_1_hw_phy_config(tp);
3123+
break;
3124+
case RTL_GIGA_MAC_VER_36:
3125+
rtl8168f_2_hw_phy_config(tp);
3126+
break;
30033127

30043128
default:
30053129
break;
@@ -3535,6 +3659,8 @@ static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
35353659
case RTL_GIGA_MAC_VER_32:
35363660
case RTL_GIGA_MAC_VER_33:
35373661
case RTL_GIGA_MAC_VER_34:
3662+
case RTL_GIGA_MAC_VER_35:
3663+
case RTL_GIGA_MAC_VER_36:
35383664
ops->down = r8168_pll_power_down;
35393665
ops->up = r8168_pll_power_up;
35403666
break;
@@ -4009,7 +4135,9 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp)
40094135
tp->mac_version == RTL_GIGA_MAC_VER_31) {
40104136
while (RTL_R8(TxPoll) & NPQ)
40114137
udelay(20);
4012-
} else if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
4138+
} else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4139+
tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4140+
tp->mac_version == RTL_GIGA_MAC_VER_36) {
40134141
RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
40144142
while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
40154143
udelay(100);
@@ -4495,6 +4623,49 @@ static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
44954623
RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
44964624
}
44974625

4626+
static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4627+
{
4628+
static const struct ephy_info e_info_8168f_1[] = {
4629+
{ 0x06, 0x00c0, 0x0020 },
4630+
{ 0x08, 0x0001, 0x0002 },
4631+
{ 0x09, 0x0000, 0x0080 },
4632+
{ 0x19, 0x0000, 0x0224 }
4633+
};
4634+
4635+
rtl_csi_access_enable_1(ioaddr);
4636+
4637+
rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4638+
4639+
rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4640+
4641+
rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4642+
rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4643+
rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4644+
rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4645+
rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4646+
rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4647+
rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4648+
rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4649+
rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4650+
rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4651+
rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4652+
ERIAR_EXGMAC);
4653+
4654+
RTL_W8(MaxTxPacketSize, EarlySize);
4655+
4656+
rtl_disable_clock_request(pdev);
4657+
4658+
RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4659+
RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4660+
4661+
/* Adjust EEE LED frequency */
4662+
RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4663+
4664+
RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4665+
RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4666+
RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4667+
}
4668+
44984669
static void rtl_hw_start_8168(struct net_device *dev)
44994670
{
45004671
struct rtl8169_private *tp = netdev_priv(dev);
@@ -4589,6 +4760,11 @@ static void rtl_hw_start_8168(struct net_device *dev)
45894760
rtl_hw_start_8168e_2(ioaddr, pdev);
45904761
break;
45914762

4763+
case RTL_GIGA_MAC_VER_35:
4764+
case RTL_GIGA_MAC_VER_36:
4765+
rtl_hw_start_8168f_1(ioaddr, pdev);
4766+
break;
4767+
45924768
default:
45934769
printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
45944770
dev->name, tp->mac_version);

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