@@ -165,12 +165,6 @@ enum i2c_slave_read_status {
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I2C_SLAVE_RX_END ,
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};
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- enum i2c_slave_xfer_dir {
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- I2C_SLAVE_DIR_READ = 0 ,
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- I2C_SLAVE_DIR_WRITE ,
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- I2C_SLAVE_DIR_NONE ,
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- };
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-
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enum bus_speed_index {
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I2C_SPD_100K = 0 ,
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I2C_SPD_400K ,
@@ -203,7 +197,6 @@ struct bcm_iproc_i2c_dev {
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struct i2c_msg * msg ;
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struct i2c_client * slave ;
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- enum i2c_slave_xfer_dir xfer_dir ;
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/* bytes that have been transferred */
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unsigned int tx_bytes ;
@@ -219,7 +212,8 @@ struct bcm_iproc_i2c_dev {
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| BIT(IS_M_RX_THLD_SHIFT))
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#define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
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- | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT))
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+ | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
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+ | BIT(IS_S_TX_UNDERRUN_SHIFT))
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static int bcm_iproc_i2c_reg_slave (struct i2c_client * slave );
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static int bcm_iproc_i2c_unreg_slave (struct i2c_client * slave );
@@ -297,15 +291,11 @@ static void bcm_iproc_i2c_slave_init(
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/* clear all pending slave interrupts */
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iproc_i2c_wr_reg (iproc_i2c , IS_OFFSET , ISR_MASK_SLAVE );
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- /* Enable interrupt register for any READ event */
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- val = BIT (IE_S_RD_EVENT_SHIFT );
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/* Enable interrupt register to indicate a valid byte in receive fifo */
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- val | = BIT (IE_S_RX_EVENT_SHIFT );
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+ val = BIT (IE_S_RX_EVENT_SHIFT );
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/* Enable interrupt register for the Slave BUSY command */
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val |= BIT (IE_S_START_BUSY_SHIFT );
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iproc_i2c_wr_reg (iproc_i2c , IE_OFFSET , val );
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-
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- iproc_i2c -> xfer_dir = I2C_SLAVE_DIR_NONE ;
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}
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static void bcm_iproc_i2c_check_slave_status (
@@ -314,8 +304,11 @@ static void bcm_iproc_i2c_check_slave_status(
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u32 val ;
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val = iproc_i2c_rd_reg (iproc_i2c , S_CMD_OFFSET );
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- val = (val >> S_CMD_STATUS_SHIFT ) & S_CMD_STATUS_MASK ;
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+ /* status is valid only when START_BUSY is cleared after it was set */
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+ if (val & BIT (S_CMD_START_BUSY_SHIFT ))
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+ return ;
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+ val = (val >> S_CMD_STATUS_SHIFT ) & S_CMD_STATUS_MASK ;
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if (val == S_CMD_STATUS_TIMEOUT ) {
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dev_err (iproc_i2c -> device , "slave random stretch time timeout\n" );
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@@ -327,70 +320,66 @@ static void bcm_iproc_i2c_check_slave_status(
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}
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static bool bcm_iproc_i2c_slave_isr (struct bcm_iproc_i2c_dev * iproc_i2c ,
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- u32 status )
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+ u32 status )
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{
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- u8 value ;
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u32 val ;
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- u32 rd_status ;
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- u32 tmp ;
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+ u8 value , rx_status ;
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- /* Start of transaction. check address and populate the direction */
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- if (iproc_i2c -> xfer_dir == I2C_SLAVE_DIR_NONE ) {
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- tmp = iproc_i2c_rd_reg (iproc_i2c , S_RX_OFFSET );
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- rd_status = (tmp >> S_RX_STATUS_SHIFT ) & S_RX_STATUS_MASK ;
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- /* This condition checks whether the request is a new request */
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- if (((rd_status == I2C_SLAVE_RX_START ) &&
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- (status & BIT (IS_S_RX_EVENT_SHIFT ))) ||
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- ((rd_status == I2C_SLAVE_RX_END ) &&
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- (status & BIT (IS_S_RD_EVENT_SHIFT )))) {
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-
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- /* Last bit is W/R bit.
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- * If 1 then its a read request(by master).
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- */
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- iproc_i2c -> xfer_dir = tmp & SLAVE_READ_WRITE_BIT_MASK ;
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- if (iproc_i2c -> xfer_dir == I2C_SLAVE_DIR_WRITE )
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- i2c_slave_event (iproc_i2c -> slave ,
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- I2C_SLAVE_READ_REQUESTED , & value );
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- else
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- i2c_slave_event (iproc_i2c -> slave ,
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+ /* Slave RX byte receive */
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+ if (status & BIT (IS_S_RX_EVENT_SHIFT )) {
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+ val = iproc_i2c_rd_reg (iproc_i2c , S_RX_OFFSET );
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+ rx_status = (val >> S_RX_STATUS_SHIFT ) & S_RX_STATUS_MASK ;
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+ if (rx_status == I2C_SLAVE_RX_START ) {
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+ /* Start of SMBUS for Master write */
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+ i2c_slave_event (iproc_i2c -> slave ,
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I2C_SLAVE_WRITE_REQUESTED , & value );
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- }
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- }
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- /* read request from master */
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- if ((status & BIT (IS_S_RD_EVENT_SHIFT )) &&
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- (iproc_i2c -> xfer_dir == I2C_SLAVE_DIR_WRITE )) {
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- i2c_slave_event (iproc_i2c -> slave ,
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- I2C_SLAVE_READ_PROCESSED , & value );
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- iproc_i2c_wr_reg (iproc_i2c , S_TX_OFFSET , value );
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+ val = iproc_i2c_rd_reg (iproc_i2c , S_RX_OFFSET );
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+ value = (u8 )((val >> S_RX_DATA_SHIFT ) & S_RX_DATA_MASK );
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+ i2c_slave_event (iproc_i2c -> slave ,
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+ I2C_SLAVE_WRITE_RECEIVED , & value );
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+ } else if (status & BIT (IS_S_RD_EVENT_SHIFT )) {
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+ /* Start of SMBUS for Master Read */
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+ i2c_slave_event (iproc_i2c -> slave ,
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+ I2C_SLAVE_READ_REQUESTED , & value );
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+ iproc_i2c_wr_reg (iproc_i2c , S_TX_OFFSET , value );
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- val = BIT (S_CMD_START_BUSY_SHIFT );
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- iproc_i2c_wr_reg (iproc_i2c , S_CMD_OFFSET , val );
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- }
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+ val = BIT (S_CMD_START_BUSY_SHIFT );
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+ iproc_i2c_wr_reg (iproc_i2c , S_CMD_OFFSET , val );
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- /* write request from master */
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- if ((status & BIT (IS_S_RX_EVENT_SHIFT )) &&
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- (iproc_i2c -> xfer_dir == I2C_SLAVE_DIR_READ )) {
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- val = iproc_i2c_rd_reg (iproc_i2c , S_RX_OFFSET );
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- /* Its a write request by Master to Slave.
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- * We read data present in receive FIFO
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- */
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- value = (u8 )((val >> S_RX_DATA_SHIFT ) & S_RX_DATA_MASK );
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+ /*
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+ * Enable interrupt for TX FIFO becomes empty and
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+ * less than PKT_LENGTH bytes were output on the SMBUS
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+ */
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+ val = iproc_i2c_rd_reg (iproc_i2c , IE_OFFSET );
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+ val |= BIT (IE_S_TX_UNDERRUN_SHIFT );
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+ iproc_i2c_wr_reg (iproc_i2c , IE_OFFSET , val );
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+ } else {
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+ /* Master write other than start */
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+ value = (u8 )((val >> S_RX_DATA_SHIFT ) & S_RX_DATA_MASK );
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+ i2c_slave_event (iproc_i2c -> slave ,
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+ I2C_SLAVE_WRITE_RECEIVED , & value );
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+ }
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+ } else if (status & BIT (IS_S_TX_UNDERRUN_SHIFT )) {
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+ /* Master read other than start */
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i2c_slave_event (iproc_i2c -> slave ,
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- I2C_SLAVE_WRITE_RECEIVED , & value );
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-
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- /* check the status for the last byte of the transaction */
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- rd_status = (val >> S_RX_STATUS_SHIFT ) & S_RX_STATUS_MASK ;
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- if (rd_status == I2C_SLAVE_RX_END )
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- iproc_i2c -> xfer_dir = I2C_SLAVE_DIR_NONE ;
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+ I2C_SLAVE_READ_PROCESSED , & value );
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- dev_dbg (iproc_i2c -> device , "\nread value = 0x%x\n" , value );
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+ iproc_i2c_wr_reg (iproc_i2c , S_TX_OFFSET , value );
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+ val = BIT (S_CMD_START_BUSY_SHIFT );
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+ iproc_i2c_wr_reg (iproc_i2c , S_CMD_OFFSET , val );
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}
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/* Stop */
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if (status & BIT (IS_S_START_BUSY_SHIFT )) {
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i2c_slave_event (iproc_i2c -> slave , I2C_SLAVE_STOP , & value );
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- iproc_i2c -> xfer_dir = I2C_SLAVE_DIR_NONE ;
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+ /*
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+ * Enable interrupt for TX FIFO becomes empty and
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+ * less than PKT_LENGTH bytes were output on the SMBUS
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+ */
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+ val = iproc_i2c_rd_reg (iproc_i2c , IE_OFFSET );
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+ val &= ~BIT (IE_S_TX_UNDERRUN_SHIFT );
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+ iproc_i2c_wr_reg (iproc_i2c , IE_OFFSET , val );
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}
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/* clear interrupt status */
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