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rayagondaWolfram Sang
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i2c: iproc: Add multi byte read-write support for slave mode
Add multiple byte read-write support for slave mode. Signed-off-by: Rayagonda Kokatanur <[email protected]> Signed-off-by: Srinath Mannam <[email protected]> Reviewed-by: Ray Jui <[email protected]> Signed-off-by: Wolfram Sang <[email protected]>
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drivers/i2c/busses/i2c-bcm-iproc.c

Lines changed: 53 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -165,12 +165,6 @@ enum i2c_slave_read_status {
165165
I2C_SLAVE_RX_END,
166166
};
167167

168-
enum i2c_slave_xfer_dir {
169-
I2C_SLAVE_DIR_READ = 0,
170-
I2C_SLAVE_DIR_WRITE,
171-
I2C_SLAVE_DIR_NONE,
172-
};
173-
174168
enum bus_speed_index {
175169
I2C_SPD_100K = 0,
176170
I2C_SPD_400K,
@@ -203,7 +197,6 @@ struct bcm_iproc_i2c_dev {
203197
struct i2c_msg *msg;
204198

205199
struct i2c_client *slave;
206-
enum i2c_slave_xfer_dir xfer_dir;
207200

208201
/* bytes that have been transferred */
209202
unsigned int tx_bytes;
@@ -219,7 +212,8 @@ struct bcm_iproc_i2c_dev {
219212
| BIT(IS_M_RX_THLD_SHIFT))
220213

221214
#define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
222-
| BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT))
215+
| BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
216+
| BIT(IS_S_TX_UNDERRUN_SHIFT))
223217

224218
static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
225219
static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
@@ -297,15 +291,11 @@ static void bcm_iproc_i2c_slave_init(
297291
/* clear all pending slave interrupts */
298292
iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
299293

300-
/* Enable interrupt register for any READ event */
301-
val = BIT(IE_S_RD_EVENT_SHIFT);
302294
/* Enable interrupt register to indicate a valid byte in receive fifo */
303-
val |= BIT(IE_S_RX_EVENT_SHIFT);
295+
val = BIT(IE_S_RX_EVENT_SHIFT);
304296
/* Enable interrupt register for the Slave BUSY command */
305297
val |= BIT(IE_S_START_BUSY_SHIFT);
306298
iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
307-
308-
iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE;
309299
}
310300

311301
static void bcm_iproc_i2c_check_slave_status(
@@ -314,8 +304,11 @@ static void bcm_iproc_i2c_check_slave_status(
314304
u32 val;
315305

316306
val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
317-
val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
307+
/* status is valid only when START_BUSY is cleared after it was set */
308+
if (val & BIT(S_CMD_START_BUSY_SHIFT))
309+
return;
318310

311+
val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
319312
if (val == S_CMD_STATUS_TIMEOUT) {
320313
dev_err(iproc_i2c->device, "slave random stretch time timeout\n");
321314

@@ -327,70 +320,66 @@ static void bcm_iproc_i2c_check_slave_status(
327320
}
328321

329322
static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
330-
u32 status)
323+
u32 status)
331324
{
332-
u8 value;
333325
u32 val;
334-
u32 rd_status;
335-
u32 tmp;
326+
u8 value, rx_status;
336327

337-
/* Start of transaction. check address and populate the direction */
338-
if (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_NONE) {
339-
tmp = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
340-
rd_status = (tmp >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
341-
/* This condition checks whether the request is a new request */
342-
if (((rd_status == I2C_SLAVE_RX_START) &&
343-
(status & BIT(IS_S_RX_EVENT_SHIFT))) ||
344-
((rd_status == I2C_SLAVE_RX_END) &&
345-
(status & BIT(IS_S_RD_EVENT_SHIFT)))) {
346-
347-
/* Last bit is W/R bit.
348-
* If 1 then its a read request(by master).
349-
*/
350-
iproc_i2c->xfer_dir = tmp & SLAVE_READ_WRITE_BIT_MASK;
351-
if (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_WRITE)
352-
i2c_slave_event(iproc_i2c->slave,
353-
I2C_SLAVE_READ_REQUESTED, &value);
354-
else
355-
i2c_slave_event(iproc_i2c->slave,
328+
/* Slave RX byte receive */
329+
if (status & BIT(IS_S_RX_EVENT_SHIFT)) {
330+
val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
331+
rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
332+
if (rx_status == I2C_SLAVE_RX_START) {
333+
/* Start of SMBUS for Master write */
334+
i2c_slave_event(iproc_i2c->slave,
356335
I2C_SLAVE_WRITE_REQUESTED, &value);
357-
}
358-
}
359336

360-
/* read request from master */
361-
if ((status & BIT(IS_S_RD_EVENT_SHIFT)) &&
362-
(iproc_i2c->xfer_dir == I2C_SLAVE_DIR_WRITE)) {
363-
i2c_slave_event(iproc_i2c->slave,
364-
I2C_SLAVE_READ_PROCESSED, &value);
365-
iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
337+
val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
338+
value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
339+
i2c_slave_event(iproc_i2c->slave,
340+
I2C_SLAVE_WRITE_RECEIVED, &value);
341+
} else if (status & BIT(IS_S_RD_EVENT_SHIFT)) {
342+
/* Start of SMBUS for Master Read */
343+
i2c_slave_event(iproc_i2c->slave,
344+
I2C_SLAVE_READ_REQUESTED, &value);
345+
iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
366346

367-
val = BIT(S_CMD_START_BUSY_SHIFT);
368-
iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
369-
}
347+
val = BIT(S_CMD_START_BUSY_SHIFT);
348+
iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
370349

371-
/* write request from master */
372-
if ((status & BIT(IS_S_RX_EVENT_SHIFT)) &&
373-
(iproc_i2c->xfer_dir == I2C_SLAVE_DIR_READ)) {
374-
val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
375-
/* Its a write request by Master to Slave.
376-
* We read data present in receive FIFO
377-
*/
378-
value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
350+
/*
351+
* Enable interrupt for TX FIFO becomes empty and
352+
* less than PKT_LENGTH bytes were output on the SMBUS
353+
*/
354+
val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
355+
val |= BIT(IE_S_TX_UNDERRUN_SHIFT);
356+
iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
357+
} else {
358+
/* Master write other than start */
359+
value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
360+
i2c_slave_event(iproc_i2c->slave,
361+
I2C_SLAVE_WRITE_RECEIVED, &value);
362+
}
363+
} else if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
364+
/* Master read other than start */
379365
i2c_slave_event(iproc_i2c->slave,
380-
I2C_SLAVE_WRITE_RECEIVED, &value);
381-
382-
/* check the status for the last byte of the transaction */
383-
rd_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
384-
if (rd_status == I2C_SLAVE_RX_END)
385-
iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE;
366+
I2C_SLAVE_READ_PROCESSED, &value);
386367

387-
dev_dbg(iproc_i2c->device, "\nread value = 0x%x\n", value);
368+
iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
369+
val = BIT(S_CMD_START_BUSY_SHIFT);
370+
iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
388371
}
389372

390373
/* Stop */
391374
if (status & BIT(IS_S_START_BUSY_SHIFT)) {
392375
i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
393-
iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE;
376+
/*
377+
* Enable interrupt for TX FIFO becomes empty and
378+
* less than PKT_LENGTH bytes were output on the SMBUS
379+
*/
380+
val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
381+
val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
382+
iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
394383
}
395384

396385
/* clear interrupt status */

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