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Merge branches 'clk-range', 'clk-uniphier', 'clk-apple' and 'clk-qcom' into clk-next
 - Make clk_set_rate_range() re-evaluate the limits each time - Introduce various clk_set_rate_range() tests - Add clk_drop_range() to drop a previously set range - Support for NCO blocks on Apple SoCs * clk-range: clk: Drop the rate range on clk_put() clk: test: Test clk_set_rate_range on orphan mux clk: Initialize orphan req_rate clk: bcm: rpi: Run some clocks at the minimum rate allowed clk: bcm: rpi: Set a default minimum rate clk: bcm: rpi: Add variant structure clk: Add clk_drop_range clk: Always set the rate on clk_set_range_rate clk: Use clamp instead of open-coding our own clk: Always clamp the rounded rate clk: Enforce that disjoints limits are invalid clk: Introduce Kunit Tests for the framework clk: Fix clk_hw_get_clk() when dev is NULL * clk-uniphier: clk: uniphier: Fix fixed-rate initialization * clk-apple: clk: clk-apple-nco: Allow and fix module building MAINTAINERS: Add clk-apple-nco under ARM/APPLE MACHINE clk: clk-apple-nco: Add driver for Apple NCO dt-bindings: clock: Add Apple NCO * clk-qcom: (61 commits) clk: qcom: gcc-msm8994: Fix gpll4 width dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml clk: qcom: Add display clock controller driver for SM6125 dt-bindings: clock: add QCOM SM6125 display clock bindings clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig clk: qcom: gcc: Add emac GDSC support for SM8150 clk: qcom: gcc: sm8150: Fix some identation issues clk: qcom: gcc: Add UFS_CARD and UFS_PHY GDSCs for SM8150 clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150 clk: qcom: clk-rcg2: Update the frac table for pixel clock clk: qcom: clk-rcg2: Update logic to calculate D value for RCG clk: qcom: smd: Add missing MSM8998 RPM clocks clk: qcom: smd: Add missing RPM clocks for msm8992/4 dt-bindings: clock: qcom: rpmcc: Add RPM Modem SubSystem (MSS) clocks clk: qcom: gcc-ipq806x: add CryptoEngine resets dt-bindings: reset: add ipq8064 ce5 resets clk: qcom: gcc-ipq806x: add CryptoEngine clocks dt-bindings: clock: add ipq8064 ce5 clk define clk: qcom: gcc-ipq806x: add additional freq for sdc table clk: qcom: clk-rcg: add clk_rcg_floor_ops ops ...
5 parents 4222744 + 7dabfa2 + ca85a66 + 236541a + 71021db commit c64dd8e

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‎Documentation/devicetree/bindings/clock/apple,nco.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/apple,nco.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Apple SoCs' NCO block
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maintainers:
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- Martin Povišer <[email protected]>
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description: |
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The NCO (Numerically Controlled Oscillator) block found on Apple SoCs
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such as the t8103 (M1) is a programmable clock generator performing
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fractional division of a high frequency input clock.
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It carries a number of independent channels and is typically used for
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generation of audio bitclocks.
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properties:
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compatible:
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items:
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- enum:
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- apple,t6000-nco
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- apple,t8103-nco
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- const: apple,nco
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clocks:
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description:
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Specifies the reference clock from which the output clocks
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are derived through fractional division.
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maxItems: 1
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'#clock-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- clocks
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- '#clock-cells'
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- reg
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additionalProperties: false
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examples:
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- |
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nco_clkref: clock-ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <900000000>;
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clock-output-names = "nco-ref";
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};
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nco: clock-controller@23b044000 {
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compatible = "apple,t8103-nco", "apple,nco";
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reg = <0x3b044000 0x14000>;
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#clock-cells = <1>;
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clocks = <&nco_clkref>;
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};

‎Documentation/devicetree/bindings/clock/qcom,a7pll.yaml

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- Manivannan Sadhasivam <[email protected]>
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description:
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The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
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The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
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frequency clock to the CPU.
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properties:

‎Documentation/devicetree/bindings/clock/qcom,camcc.txt

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This file was deleted.

‎Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock Controller Binding for SM6125
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maintainers:
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- Martin Botka <[email protected]>
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description: |
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Qualcomm display clock control module which supports the clocks and
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power domains on SM6125.
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See also:
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dt-bindings/clock/qcom,dispcc-sm6125.h
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properties:
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compatible:
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enum:
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- qcom,sm6125-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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- description: Pixel clock from DSI PHY1
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- description: Link clock from DP PHY
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- description: VCO DIV clock from DP PHY
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- description: AHB config clock from GCC
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clock-names:
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items:
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- const: bi_tcxo
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- const: dsi0_phy_pll_out_byteclk
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- const: dsi0_phy_pll_out_dsiclk
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- const: dsi1_phy_pll_out_dsiclk
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- const: dp_phy_pll_link_clk
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- const: dp_phy_pll_vco_div_clk
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- const: cfg_ahb_clk
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'#clock-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/clock/qcom,gcc-sm6125.h>
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clock-controller@5f00000 {
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compatible = "qcom,sm6125-dispcc";
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reg = <0x5f00000 0x20000>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&dsi0_phy 0>,
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<&dsi0_phy 1>,
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<&dsi1_phy 1>,
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<&dp_phy 0>,
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<&dp_phy 1>,
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<&gcc GCC_DISP_AHB_CLK>;
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clock-names = "bi_tcxo",
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"dsi0_phy_pll_out_byteclk",
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"dsi0_phy_pll_out_dsiclk",
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"dsi1_phy_pll_out_dsiclk",
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"dp_phy_pll_link_clk",
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"dp_phy_pll_vco_div_clk",
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"cfg_ahb_clk";
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller Binding for SM6350
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maintainers:
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- Konrad Dybcio <[email protected]>
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description: |
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Qualcomm display clock control module which supports the clocks, resets and
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power domains on SM6350.
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See also dt-bindings/clock/qcom,dispcc-sm6350.h.
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properties:
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compatible:
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const: qcom,sm6350-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 source from GCC
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- description: Byte clock from DSI PHY
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- description: Pixel clock from DSI PHY
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- description: Link clock from DP PHY
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- description: VCO DIV clock from DP PHY
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clock-names:
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items:
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- const: bi_tcxo
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- const: gcc_disp_gpll0_clk
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- const: dsi0_phy_pll_out_byteclk
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- const: dsi0_phy_pll_out_dsiclk
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- const: dp_phy_pll_link_clk
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- const: dp_phy_pll_vco_div_clk
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm6350.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@af00000 {
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compatible = "qcom,sm6350-dispcc";
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reg = <0x0af00000 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_DISP_GPLL0_CLK>,
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<&dsi_phy 0>,
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<&dsi_phy 1>,
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<&dp_phy 0>,
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<&dp_phy 1>;
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clock-names = "bi_tcxo",
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"gcc_disp_gpll0_clk",
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"dsi0_phy_pll_out_byteclk",
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"dsi0_phy_pll_out_dsiclk",
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"dp_phy_pll_link_clk",
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"dp_phy_pll_vco_div_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml

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title: Qualcomm Global Clock & Reset Controller Binding for APQ8064
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allOf:
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- $ref: qcom,gcc.yaml#
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maintainers:
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- Stephen Boyd <[email protected]>
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- Taniya Das <[email protected]>
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See also:
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- dt-bindings/clock/qcom,gcc-msm8960.h
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- dt-bindings/reset/qcom,gcc-msm8960.h
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- dt-bindings/clock/qcom,gcc-apq8084.h
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- dt-bindings/reset/qcom,gcc-apq8084.h
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properties:
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compatible:
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const: qcom,gcc-apq8064
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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const: qcom,gcc-apq8084
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nvmem-cells:
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minItems: 1
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'#thermal-sensor-cells':
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const: 1
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protected-clocks:
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description:
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Protected clock specifier list as per common clock binding.
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required:
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- compatible
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- reg
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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- nvmem-cells
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- nvmem-cell-names
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- '#thermal-sensor-cells'
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additionalProperties: false
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unevaluatedProperties: false
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examples:
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- |

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