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Merge tag 'amd-drm-next-5.14-2021-06-09' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-5.14-2021-06-09: amdgpu: - SR-IOV fixes - Smartshift updates - GPUVM TLB flush updates - 16bpc fixed point display fix for DCE11 - BACO cleanups and core refactoring - Aldebaran updates - Initial Yellow Carp support - RAS fixes - PM API cleanup - DC visual confirm updates - DC DP MST fixes - DC DML fixes - Misc code cleanups and bug fixes amdkfd: - Initial Yellow Carp support radeon: - memcpy_to/from_io fixes UAPI: - Add Yellow Carp chip family id Used internally in the kernel driver and by mesa Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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‎Documentation/gpu/amdgpu.rst

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -300,4 +300,25 @@ pcie_replay_count
300300
.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
301301
:doc: pcie_replay_count
302302

303+
+GPU SmartShift Information
304+
============================
305+
306+
GPU SmartShift information via sysfs
307+
308+
smartshift_apu_power
309+
--------------------
310+
311+
.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
312+
:doc: smartshift_apu_power
303313

314+
smartshift_dgpu_power
315+
---------------------
316+
317+
.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
318+
:doc: smartshift_dgpu_power
319+
320+
smartshift_bias
321+
---------------
322+
323+
.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
324+
:doc: smartshift_bias

‎drivers/gpu/drm/amd/amdgpu/Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -75,7 +75,7 @@ amdgpu-y += \
7575
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
7676
arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o \
7777
nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o \
78-
beige_goby_reg_init.o
78+
beige_goby_reg_init.o yellow_carp_reg_init.o
7979

8080
# add DF block
8181
amdgpu-y += \

‎drivers/gpu/drm/amd/amdgpu/amdgpu.h

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -211,6 +211,7 @@ extern int amdgpu_discovery;
211211
extern int amdgpu_mes;
212212
extern int amdgpu_noretry;
213213
extern int amdgpu_force_asic_type;
214+
extern int amdgpu_smartshift_bias;
214215
#ifdef CONFIG_HSA_AMD
215216
extern int sched_policy;
216217
extern bool debug_evictions;
@@ -268,6 +269,10 @@ extern int amdgpu_num_kcq;
268269
#define CIK_CURSOR_WIDTH 128
269270
#define CIK_CURSOR_HEIGHT 128
270271

272+
/* smasrt shift bias level limits */
273+
#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
274+
#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
275+
271276
struct amdgpu_device;
272277
struct amdgpu_ib;
273278
struct amdgpu_cs_parser;
@@ -1280,6 +1285,11 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
12801285
int amdgpu_device_baco_enter(struct drm_device *dev);
12811286
int amdgpu_device_baco_exit(struct drm_device *dev);
12821287

1288+
void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1289+
struct amdgpu_ring *ring);
1290+
void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1291+
struct amdgpu_ring *ring);
1292+
12831293
/* atpx handler */
12841294
#if defined(CONFIG_VGA_SWITCHEROO)
12851295
void amdgpu_register_atpx_handler(void);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -269,7 +269,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
269269
struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv,
270270
uint64_t *size);
271271
int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
272-
struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
272+
struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv, bool *table_freed);
273273
int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
274274
struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
275275
int amdgpu_amdkfd_gpuvm_sync_memory(

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -95,8 +95,8 @@ static void program_sh_mem_settings_v10_3(struct kgd_dev *kgd, uint32_t vmid,
9595

9696
lock_srbm(kgd, 0, 0, 0, vmid);
9797

98-
WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
99-
WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
98+
WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
99+
WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
100100
/* APE1 no longer exists on GFX9 */
101101

102102
unlock_srbm(kgd);
@@ -129,7 +129,7 @@ static int init_interrupts_v10_3(struct kgd_dev *kgd, uint32_t pipe_id)
129129

130130
lock_srbm(kgd, mec, pipe, 0, 0);
131131

132-
WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
132+
WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
133133
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
134134
CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
135135

@@ -212,10 +212,10 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
212212

213213
pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
214214
mec, pipe, queue_id);
215-
value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS));
215+
value = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
216216
value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
217217
((mec << 5) | (pipe << 3) | queue_id | 0x80));
218-
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value);
218+
WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, value);
219219
}
220220

221221
/* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
@@ -224,13 +224,13 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
224224

225225
for (reg = hqd_base;
226226
reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
227-
WREG32(reg, mqd_hqd[reg - hqd_base]);
227+
WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);
228228

229229

230230
/* Activate doorbell logic before triggering WPTR poll. */
231231
data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
232232
CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
233-
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
233+
WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);
234234

235235
if (wptr) {
236236
/* Don't read wptr with get_user because the user
@@ -259,17 +259,17 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
259259
guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
260260
guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
261261

262-
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
262+
WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
263263
lower_32_bits(guessed_wptr));
264-
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
264+
WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
265265
upper_32_bits(guessed_wptr));
266-
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
266+
WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
267267
lower_32_bits((uint64_t)wptr));
268-
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
268+
WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
269269
upper_32_bits((uint64_t)wptr));
270270
pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,
271271
(uint32_t)get_queue_mask(adev, pipe_id, queue_id));
272-
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
272+
WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,
273273
(uint32_t)get_queue_mask(adev, pipe_id, queue_id));
274274
}
275275

@@ -279,7 +279,7 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
279279
CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
280280

281281
data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
282-
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
282+
WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data);
283283

284284
release_queue(kgd);
285285

@@ -350,7 +350,7 @@ static int hqd_dump_v10_3(struct kgd_dev *kgd,
350350
if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
351351
break; \
352352
(*dump)[i][0] = (addr) << 2; \
353-
(*dump)[i++][1] = RREG32(addr); \
353+
(*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \
354354
} while (0)
355355

356356
*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
@@ -482,13 +482,13 @@ static bool hqd_is_occupied_v10_3(struct kgd_dev *kgd, uint64_t queue_address,
482482
uint32_t low, high;
483483

484484
acquire_queue(kgd, pipe_id, queue_id);
485-
act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
485+
act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
486486
if (act) {
487487
low = lower_32_bits(queue_address >> 8);
488488
high = upper_32_bits(queue_address >> 8);
489489

490-
if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
491-
high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
490+
if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&
491+
high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))
492492
retval = true;
493493
}
494494
release_queue(kgd);
@@ -542,11 +542,11 @@ static int hqd_destroy_v10_3(struct kgd_dev *kgd, void *mqd,
542542
break;
543543
}
544544

545-
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);
545+
WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type);
546546

547547
end_jiffies = (utimeout * HZ / 1000) + jiffies;
548548
while (true) {
549-
temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
549+
temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
550550
if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
551551
break;
552552
if (time_after(jiffies, end_jiffies)) {
@@ -626,7 +626,7 @@ static int wave_control_execute_v10_3(struct kgd_dev *kgd,
626626

627627
mutex_lock(&adev->grbm_idx_mutex);
628628

629-
WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val);
629+
WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);
630630
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
631631

632632
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
@@ -636,7 +636,7 @@ static int wave_control_execute_v10_3(struct kgd_dev *kgd,
636636
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
637637
SE_BROADCAST_WRITES, 1);
638638

639-
WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);
639+
WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
640640
mutex_unlock(&adev->grbm_idx_mutex);
641641

642642
return 0;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

Lines changed: 12 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -278,7 +278,7 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
278278
write_seqcount_end(&resv->seq);
279279

280280
/* Drop the references to the removed fences or move them to ef_list */
281-
for (i = j, k = 0; i < old->shared_count; ++i) {
281+
for (i = j; i < old->shared_count; ++i) {
282282
struct dma_fence *f;
283283

284284
f = rcu_dereference_protected(new->shared[i],
@@ -1070,7 +1070,8 @@ static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
10701070

10711071
static int update_gpuvm_pte(struct kgd_mem *mem,
10721072
struct kfd_mem_attachment *entry,
1073-
struct amdgpu_sync *sync)
1073+
struct amdgpu_sync *sync,
1074+
bool *table_freed)
10741075
{
10751076
struct amdgpu_bo_va *bo_va = entry->bo_va;
10761077
struct amdgpu_device *adev = entry->adev;
@@ -1081,7 +1082,7 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
10811082
return ret;
10821083

10831084
/* Update the page tables */
1084-
ret = amdgpu_vm_bo_update(adev, bo_va, false);
1085+
ret = amdgpu_vm_bo_update(adev, bo_va, false, table_freed);
10851086
if (ret) {
10861087
pr_err("amdgpu_vm_bo_update failed\n");
10871088
return ret;
@@ -1093,7 +1094,8 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
10931094
static int map_bo_to_gpuvm(struct kgd_mem *mem,
10941095
struct kfd_mem_attachment *entry,
10951096
struct amdgpu_sync *sync,
1096-
bool no_update_pte)
1097+
bool no_update_pte,
1098+
bool *table_freed)
10971099
{
10981100
int ret;
10991101

@@ -1110,7 +1112,7 @@ static int map_bo_to_gpuvm(struct kgd_mem *mem,
11101112
if (no_update_pte)
11111113
return 0;
11121114

1113-
ret = update_gpuvm_pte(mem, entry, sync);
1115+
ret = update_gpuvm_pte(mem, entry, sync, table_freed);
11141116
if (ret) {
11151117
pr_err("update_gpuvm_pte() failed\n");
11161118
goto update_gpuvm_pte_failed;
@@ -1608,7 +1610,8 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
16081610
}
16091611

16101612
int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1611-
struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv)
1613+
struct kgd_dev *kgd, struct kgd_mem *mem,
1614+
void *drm_priv, bool *table_freed)
16121615
{
16131616
struct amdgpu_device *adev = get_amdgpu_device(kgd);
16141617
struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
@@ -1696,7 +1699,7 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
16961699
entry->va, entry->va + bo_size, entry);
16971700

16981701
ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
1699-
is_invalid_userptr);
1702+
is_invalid_userptr, table_freed);
17001703
if (ret) {
17011704
pr_err("Failed to map bo to gpuvm\n");
17021705
goto out_unreserve;
@@ -2146,7 +2149,7 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
21462149
continue;
21472150

21482151
kfd_mem_dmaunmap_attachment(mem, attachment);
2149-
ret = update_gpuvm_pte(mem, attachment, &sync);
2152+
ret = update_gpuvm_pte(mem, attachment, &sync, NULL);
21502153
if (ret) {
21512154
pr_err("%s: update PTE failed\n", __func__);
21522155
/* make sure this gets validated again */
@@ -2352,7 +2355,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
23522355
continue;
23532356

23542357
kfd_mem_dmaunmap_attachment(mem, attachment);
2355-
ret = update_gpuvm_pte(mem, attachment, &sync_obj);
2358+
ret = update_gpuvm_pte(mem, attachment, &sync_obj, NULL);
23562359
if (ret) {
23572360
pr_debug("Memory eviction: update PTE failed. Try again\n");
23582361
goto validate_map_fail;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -662,7 +662,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
662662
* @error: error number
663663
* @backoff: indicator to backoff the reservation
664664
*
665-
* If error is set than unvalidate buffer, otherwise just free memory
665+
* If error is set then unvalidate buffer, otherwise just free memory
666666
* used by parsing context.
667667
**/
668668
static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
@@ -781,7 +781,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
781781
if (r)
782782
return r;
783783

784-
r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
784+
r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false, NULL);
785785
if (r)
786786
return r;
787787

@@ -792,7 +792,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
792792
if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
793793
bo_va = fpriv->csa_va;
794794
BUG_ON(!bo_va);
795-
r = amdgpu_vm_bo_update(adev, bo_va, false);
795+
r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
796796
if (r)
797797
return r;
798798

@@ -811,7 +811,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
811811
if (bo_va == NULL)
812812
continue;
813813

814-
r = amdgpu_vm_bo_update(adev, bo_va, false);
814+
r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
815815
if (r)
816816
return r;
817817

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