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octeon_ep_vf: Add driver framework and device initialization
Add driver framework and device setup and initialization for Octeon PCI Endpoint NIC VF. Add implementation to load module, initialize, register network device, cleanup and unload module. Signed-off-by: Shinas Rasheed <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎Documentation/networking/device_drivers/ethernet/index.rst

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intel/ice
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marvell/octeontx2
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marvell/octeon_ep
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marvell/octeon_ep_vf
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mellanox/mlx5/index
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microsoft/netvsc
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neterion/s2io

‎Documentation/networking/device_drivers/ethernet/marvell/octeon_ep_vf.rst

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.. SPDX-License-Identifier: GPL-2.0+
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=======================================================================
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Linux kernel networking driver for Marvell's Octeon PCI Endpoint NIC VF
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=======================================================================
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Network driver for Marvell's Octeon PCI EndPoint NIC VF.
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Copyright (c) 2020 Marvell International Ltd.
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Overview
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========
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This driver implements networking functionality of Marvell's Octeon PCI
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EndPoint NIC VF.
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Supported Devices
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=================
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Currently, this driver support following devices:
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* Network controller: Cavium, Inc. Device b203
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* Network controller: Cavium, Inc. Device b403
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* Network controller: Cavium, Inc. Device b103
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* Network controller: Cavium, Inc. Device b903
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* Network controller: Cavium, Inc. Device ba03
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* Network controller: Cavium, Inc. Device bc03
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* Network controller: Cavium, Inc. Device bd03

‎drivers/net/ethernet/marvell/Kconfig

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source "drivers/net/ethernet/marvell/octeontx2/Kconfig"
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source "drivers/net/ethernet/marvell/octeon_ep/Kconfig"
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source "drivers/net/ethernet/marvell/octeon_ep_vf/Kconfig"
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source "drivers/net/ethernet/marvell/prestera/Kconfig"
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endif # NET_VENDOR_MARVELL

‎drivers/net/ethernet/marvell/Makefile

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@@ -12,5 +12,6 @@ obj-$(CONFIG_PXA168_ETH) += pxa168_eth.o
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obj-$(CONFIG_SKGE) += skge.o
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obj-$(CONFIG_SKY2) += sky2.o
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obj-y += octeon_ep/
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obj-y += octeon_ep_vf/
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obj-y += octeontx2/
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obj-y += prestera/

‎drivers/net/ethernet/marvell/octeon_ep_vf/Kconfig

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# SPDX-License-Identifier: GPL-2.0-only
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#
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# Marvell's Octeon PCI Endpoint NIC VF Driver Configuration
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#
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config OCTEON_EP_VF
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tristate "Marvell Octeon PCI Endpoint NIC VF Driver"
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depends on 64BIT
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depends on PCI
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help
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This driver supports networking functionality of Marvell's
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Octeon PCI Endpoint NIC VF.
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To know the list of devices supported by this driver, refer
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documentation in
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<file:Documentation/networking/device_drivers/ethernet/marvell/octeon_ep_vf.rst>.
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To compile this drivers as a module, choose M here. Name of the
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module is octeon_ep_vf.

‎drivers/net/ethernet/marvell/octeon_ep_vf/Makefile

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# SPDX-License-Identifier: GPL-2.0
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#
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# Network driver for Marvell's Octeon PCI Endpoint NIC VF
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#
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obj-$(CONFIG_OCTEON_EP_VF) += octeon_ep_vf.o
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octeon_ep_vf-y := octep_vf_main.o octep_vf_cn9k.o octep_vf_cnxk.o \
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octep_vf_tx.o octep_vf_rx.o octep_vf_mbox.o

‎drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

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// SPDX-License-Identifier: GPL-2.0
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/* Marvell Octeon EP (EndPoint) VF Ethernet Driver
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*
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* Copyright (C) 2020 Marvell.
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*
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*/
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include "octep_vf_config.h"
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#include "octep_vf_main.h"
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#include "octep_vf_regs_cn9k.h"
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/* Reset all hardware Tx/Rx queues */
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static void octep_vf_reset_io_queues_cn93(struct octep_vf_device *oct)
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{
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}
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/* Initialize configuration limits and initial active config */
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static void octep_vf_init_config_cn93_vf(struct octep_vf_device *oct)
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{
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struct octep_vf_config *conf = oct->conf;
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u64 reg_val;
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reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_IN_CONTROL(0));
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conf->ring_cfg.max_io_rings = (reg_val >> CN93_VF_R_IN_CTL_RPVF_POS) &
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CN93_VF_R_IN_CTL_RPVF_MASK;
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conf->ring_cfg.active_io_rings = conf->ring_cfg.max_io_rings;
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conf->iq.num_descs = OCTEP_VF_IQ_MAX_DESCRIPTORS;
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conf->iq.instr_type = OCTEP_VF_64BYTE_INSTR;
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conf->iq.db_min = OCTEP_VF_DB_MIN;
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conf->iq.intr_threshold = OCTEP_VF_IQ_INTR_THRESHOLD;
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conf->oq.num_descs = OCTEP_VF_OQ_MAX_DESCRIPTORS;
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conf->oq.buf_size = OCTEP_VF_OQ_BUF_SIZE;
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conf->oq.refill_threshold = OCTEP_VF_OQ_REFILL_THRESHOLD;
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conf->oq.oq_intr_pkt = OCTEP_VF_OQ_INTR_PKT_THRESHOLD;
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conf->oq.oq_intr_time = OCTEP_VF_OQ_INTR_TIME_THRESHOLD;
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conf->msix_cfg.ioq_msix = conf->ring_cfg.active_io_rings;
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}
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/* Setup registers for a hardware Tx Queue */
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static void octep_vf_setup_iq_regs_cn93(struct octep_vf_device *oct, int iq_no)
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{
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}
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/* Setup registers for a hardware Rx Queue */
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static void octep_vf_setup_oq_regs_cn93(struct octep_vf_device *oct, int oq_no)
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{
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}
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/* Setup registers for a VF mailbox */
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static void octep_vf_setup_mbox_regs_cn93(struct octep_vf_device *oct, int q_no)
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{
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}
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/* Tx/Rx queue interrupt handler */
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static irqreturn_t octep_vf_ioq_intr_handler_cn93(void *data)
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{
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return IRQ_HANDLED;
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}
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/* Re-initialize Octeon hardware registers */
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static void octep_vf_reinit_regs_cn93(struct octep_vf_device *oct)
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{
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}
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/* Enable all interrupts */
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static void octep_vf_enable_interrupts_cn93(struct octep_vf_device *oct)
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{
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}
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/* Disable all interrupts */
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static void octep_vf_disable_interrupts_cn93(struct octep_vf_device *oct)
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{
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}
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/* Get new Octeon Read Index: index of descriptor that Octeon reads next. */
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static u32 octep_vf_update_iq_read_index_cn93(struct octep_vf_iq *iq)
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{
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return 0;
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}
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/* Enable a hardware Tx Queue */
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static void octep_vf_enable_iq_cn93(struct octep_vf_device *oct, int iq_no)
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{
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}
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/* Enable a hardware Rx Queue */
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static void octep_vf_enable_oq_cn93(struct octep_vf_device *oct, int oq_no)
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{
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}
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/* Enable all hardware Tx/Rx Queues assigned to VF */
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static void octep_vf_enable_io_queues_cn93(struct octep_vf_device *oct)
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{
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}
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/* Disable a hardware Tx Queue assigned to VF */
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static void octep_vf_disable_iq_cn93(struct octep_vf_device *oct, int iq_no)
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{
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}
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/* Disable a hardware Rx Queue assigned to VF */
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static void octep_vf_disable_oq_cn93(struct octep_vf_device *oct, int oq_no)
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{
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}
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/* Disable all hardware Tx/Rx Queues assigned to VF */
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static void octep_vf_disable_io_queues_cn93(struct octep_vf_device *oct)
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{
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}
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/* Dump hardware registers (including Tx/Rx queues) for debugging. */
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static void octep_vf_dump_registers_cn93(struct octep_vf_device *oct)
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{
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}
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/**
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* octep_vf_device_setup_cn93() - Setup Octeon device.
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*
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* @oct: Octeon device private data structure.
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*
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* - initialize hardware operations.
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* - get target side pcie port number for the device.
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* - set initial configuration and max limits.
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*/
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void octep_vf_device_setup_cn93(struct octep_vf_device *oct)
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{
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oct->hw_ops.setup_iq_regs = octep_vf_setup_iq_regs_cn93;
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oct->hw_ops.setup_oq_regs = octep_vf_setup_oq_regs_cn93;
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oct->hw_ops.setup_mbox_regs = octep_vf_setup_mbox_regs_cn93;
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oct->hw_ops.ioq_intr_handler = octep_vf_ioq_intr_handler_cn93;
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oct->hw_ops.reinit_regs = octep_vf_reinit_regs_cn93;
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oct->hw_ops.enable_interrupts = octep_vf_enable_interrupts_cn93;
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oct->hw_ops.disable_interrupts = octep_vf_disable_interrupts_cn93;
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oct->hw_ops.update_iq_read_idx = octep_vf_update_iq_read_index_cn93;
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oct->hw_ops.enable_iq = octep_vf_enable_iq_cn93;
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oct->hw_ops.enable_oq = octep_vf_enable_oq_cn93;
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oct->hw_ops.enable_io_queues = octep_vf_enable_io_queues_cn93;
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oct->hw_ops.disable_iq = octep_vf_disable_iq_cn93;
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oct->hw_ops.disable_oq = octep_vf_disable_oq_cn93;
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oct->hw_ops.disable_io_queues = octep_vf_disable_io_queues_cn93;
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oct->hw_ops.reset_io_queues = octep_vf_reset_io_queues_cn93;
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oct->hw_ops.dump_registers = octep_vf_dump_registers_cn93;
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octep_vf_init_config_cn93_vf(oct);
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}

‎drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

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// SPDX-License-Identifier: GPL-2.0
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/* Marvell Octeon EP (EndPoint) VF Ethernet Driver
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*
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* Copyright (C) 2020 Marvell.
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*
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*/
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include "octep_vf_config.h"
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#include "octep_vf_main.h"
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#include "octep_vf_regs_cnxk.h"
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/* Reset all hardware Tx/Rx queues */
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static void octep_vf_reset_io_queues_cnxk(struct octep_vf_device *oct)
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{
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}
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/* Initialize configuration limits and initial active config */
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static void octep_vf_init_config_cnxk_vf(struct octep_vf_device *oct)
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{
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struct octep_vf_config *conf = oct->conf;
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u64 reg_val;
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reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(0));
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conf->ring_cfg.max_io_rings = (reg_val >> CNXK_VF_R_IN_CTL_RPVF_POS) &
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CNXK_VF_R_IN_CTL_RPVF_MASK;
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conf->ring_cfg.active_io_rings = conf->ring_cfg.max_io_rings;
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conf->iq.num_descs = OCTEP_VF_IQ_MAX_DESCRIPTORS;
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conf->iq.instr_type = OCTEP_VF_64BYTE_INSTR;
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conf->iq.db_min = OCTEP_VF_DB_MIN;
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conf->iq.intr_threshold = OCTEP_VF_IQ_INTR_THRESHOLD;
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conf->oq.num_descs = OCTEP_VF_OQ_MAX_DESCRIPTORS;
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conf->oq.buf_size = OCTEP_VF_OQ_BUF_SIZE;
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conf->oq.refill_threshold = OCTEP_VF_OQ_REFILL_THRESHOLD;
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conf->oq.oq_intr_pkt = OCTEP_VF_OQ_INTR_PKT_THRESHOLD;
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conf->oq.oq_intr_time = OCTEP_VF_OQ_INTR_TIME_THRESHOLD;
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conf->oq.wmark = OCTEP_VF_OQ_WMARK_MIN;
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conf->msix_cfg.ioq_msix = conf->ring_cfg.active_io_rings;
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}
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/* Setup registers for a hardware Tx Queue */
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static void octep_vf_setup_iq_regs_cnxk(struct octep_vf_device *oct, int iq_no)
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{
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}
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/* Setup registers for a hardware Rx Queue */
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static void octep_vf_setup_oq_regs_cnxk(struct octep_vf_device *oct, int oq_no)
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{
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}
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/* Setup registers for a VF mailbox */
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static void octep_vf_setup_mbox_regs_cnxk(struct octep_vf_device *oct, int q_no)
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{
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}
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/* Tx/Rx queue interrupt handler */
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static irqreturn_t octep_vf_ioq_intr_handler_cnxk(void *data)
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{
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return IRQ_HANDLED;
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}
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/* Re-initialize Octeon hardware registers */
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static void octep_vf_reinit_regs_cnxk(struct octep_vf_device *oct)
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{
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}
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/* Enable all interrupts */
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static void octep_vf_enable_interrupts_cnxk(struct octep_vf_device *oct)
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{
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}
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/* Disable all interrupts */
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static void octep_vf_disable_interrupts_cnxk(struct octep_vf_device *oct)
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{
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}
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/* Get new Octeon Read Index: index of descriptor that Octeon reads next. */
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static u32 octep_vf_update_iq_read_index_cnxk(struct octep_vf_iq *iq)
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{
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return 0;
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}
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/* Enable a hardware Tx Queue */
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static void octep_vf_enable_iq_cnxk(struct octep_vf_device *oct, int iq_no)
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{
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}
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/* Enable a hardware Rx Queue */
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static void octep_vf_enable_oq_cnxk(struct octep_vf_device *oct, int oq_no)
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{
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}
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/* Enable all hardware Tx/Rx Queues assigned to VF */
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static void octep_vf_enable_io_queues_cnxk(struct octep_vf_device *oct)
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{
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}
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/* Disable a hardware Tx Queue assigned to VF */
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static void octep_vf_disable_iq_cnxk(struct octep_vf_device *oct, int iq_no)
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{
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}
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/* Disable a hardware Rx Queue assigned to VF */
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static void octep_vf_disable_oq_cnxk(struct octep_vf_device *oct, int oq_no)
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{
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}
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/* Disable all hardware Tx/Rx Queues assigned to VF */
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static void octep_vf_disable_io_queues_cnxk(struct octep_vf_device *oct)
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{
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}
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/* Dump hardware registers (including Tx/Rx queues) for debugging. */
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static void octep_vf_dump_registers_cnxk(struct octep_vf_device *oct)
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{
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}
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/**
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* octep_vf_device_setup_cnxk() - Setup Octeon device.
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*
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* @oct: Octeon device private data structure.
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*
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* - initialize hardware operations.
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* - get target side pcie port number for the device.
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* - set initial configuration and max limits.
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*/
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void octep_vf_device_setup_cnxk(struct octep_vf_device *oct)
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{
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oct->hw_ops.setup_iq_regs = octep_vf_setup_iq_regs_cnxk;
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oct->hw_ops.setup_oq_regs = octep_vf_setup_oq_regs_cnxk;
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oct->hw_ops.setup_mbox_regs = octep_vf_setup_mbox_regs_cnxk;
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oct->hw_ops.ioq_intr_handler = octep_vf_ioq_intr_handler_cnxk;
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oct->hw_ops.reinit_regs = octep_vf_reinit_regs_cnxk;
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oct->hw_ops.enable_interrupts = octep_vf_enable_interrupts_cnxk;
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oct->hw_ops.disable_interrupts = octep_vf_disable_interrupts_cnxk;
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oct->hw_ops.update_iq_read_idx = octep_vf_update_iq_read_index_cnxk;
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oct->hw_ops.enable_iq = octep_vf_enable_iq_cnxk;
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oct->hw_ops.enable_oq = octep_vf_enable_oq_cnxk;
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oct->hw_ops.enable_io_queues = octep_vf_enable_io_queues_cnxk;
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oct->hw_ops.disable_iq = octep_vf_disable_iq_cnxk;
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oct->hw_ops.disable_oq = octep_vf_disable_oq_cnxk;
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oct->hw_ops.disable_io_queues = octep_vf_disable_io_queues_cnxk;
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oct->hw_ops.reset_io_queues = octep_vf_reset_io_queues_cnxk;
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oct->hw_ops.dump_registers = octep_vf_dump_registers_cnxk;
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octep_vf_init_config_cnxk_vf(oct);
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}

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