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41 | 41 | #define FAN53555_MONITOR 0x05
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42 | 42 |
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43 | 43 | /* VSEL bit definitions */
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44 |
| -#define VSEL_BUCK_EN (1 << 7) |
45 |
| -#define VSEL_MODE (1 << 6) |
| 44 | +#define VSEL_BUCK_EN BIT(7) |
| 45 | +#define VSEL_MODE BIT(6) |
46 | 46 | /* Chip ID and Verison */
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47 |
| -#define DIE_ID 0x0F /* ID1 */ |
48 |
| -#define DIE_REV 0x0F /* ID2 */ |
| 47 | +#define DIE_ID 0x0F /* ID1 */ |
| 48 | +#define DIE_REV 0x0F /* ID2 */ |
49 | 49 | /* Control bit definitions */
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50 |
| -#define CTL_OUTPUT_DISCHG (1 << 7) |
51 |
| -#define CTL_SLEW_MASK (0x7 << 4) |
52 |
| -#define CTL_RESET (1 << 2) |
| 50 | +#define CTL_OUTPUT_DISCHG BIT(7) |
| 51 | +#define CTL_SLEW_MASK GENMASK(6, 4) |
| 52 | +#define CTL_RESET BIT(2) |
53 | 53 | #define CTL_MODE_VSEL0_MODE BIT(0)
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54 | 54 | #define CTL_MODE_VSEL1_MODE BIT(1)
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55 | 55 |
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56 | 56 | #define FAN53555_NVOLTAGES 64 /* Numbers of voltages */
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57 | 57 | #define FAN53526_NVOLTAGES 128
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58 | 58 |
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59 |
| -#define TCS_VSEL0_MODE (1 << 7) |
60 |
| -#define TCS_VSEL1_MODE (1 << 6) |
| 59 | +#define TCS_VSEL0_MODE BIT(7) |
| 60 | +#define TCS_VSEL1_MODE BIT(6) |
61 | 61 |
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62 | 62 | #define TCS_SLEW_MASK GENMASK(4, 3)
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63 | 63 |
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