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Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
Nothing major ready for merging yet, so mostly bug fixes below, in addition to VP3 enablement from Ilia. * 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: drm/nouveau: fix command submission to use vmalloc for big allocations drm/nouveau/bios/therm: handle vbioses with duplicate entries (mostly nva5) drm/nouveau: use MSI interrupts drm/nv50-/kms: assume analog display connected if load on any pin drm/nv50/disp: prevent false output detection on the original nv50 drm/nouveau/i2c: pass the function pointers in at creation time drm/nouveau/therm: survive to suspend/resume cycles drm/nouveau/timer: add a way to cancel alarms drm/nouveau/timer: restore the time on resume drm/nouveau/fan: restore pwm value on resume when in manual/auto mode drm/nouveau/therm: Set the correct pwm_mode upon resume drm/nouveau: require contiguous bo for framebuffer drm/nv50-/disp: use the number of dac, sor, pior rather than hardcoded values drm/nouveau: remove duplicate copy of nv44_graph_class drm/nouveau/vdec: implement support for VP3 engines drm/nouveau/core: get rid of math.h, replace log2i with order_base_2
2 parents ef25bd8 + c859074 commit d30645a

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37 files changed

+323
-145
lines changed

37 files changed

+323
-145
lines changed

‎drivers/gpu/drm/nouveau/core/core/ramht.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,6 @@
2222

2323
#include <core/object.h>
2424
#include <core/ramht.h>
25-
#include <core/math.h>
2625

2726
#include <subdev/bar.h>
2827

@@ -104,6 +103,6 @@ nouveau_ramht_new(struct nouveau_object *parent, struct nouveau_object *pargpu,
104103
if (ret)
105104
return ret;
106105

107-
ramht->bits = log2i(nv_gpuobj(ramht)->size >> 3);
106+
ramht->bits = order_base_2(nv_gpuobj(ramht)->size >> 3);
108107
return 0;
109108
}

‎drivers/gpu/drm/nouveau/core/engine/bsp/nv98.c

Lines changed: 35 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -19,16 +19,14 @@
1919
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2020
* OTHER DEALINGS IN THE SOFTWARE.
2121
*
22-
* Authors: Ben Skeggs
22+
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
2323
*/
2424

25-
#include <core/engctx.h>
26-
#include <core/class.h>
27-
25+
#include <engine/falcon.h>
2826
#include <engine/bsp.h>
2927

3028
struct nv98_bsp_priv {
31-
struct nouveau_engine base;
29+
struct nouveau_falcon base;
3230
};
3331

3432
/*******************************************************************************
@@ -37,30 +35,48 @@ struct nv98_bsp_priv {
3735

3836
static struct nouveau_oclass
3937
nv98_bsp_sclass[] = {
38+
{ 0x88b1, &nouveau_object_ofuncs },
39+
{ 0x85b1, &nouveau_object_ofuncs },
40+
{ 0x86b1, &nouveau_object_ofuncs },
4041
{},
4142
};
4243

4344
/*******************************************************************************
44-
* BSP context
45+
* PBSP context
4546
******************************************************************************/
4647

4748
static struct nouveau_oclass
4849
nv98_bsp_cclass = {
4950
.handle = NV_ENGCTX(BSP, 0x98),
5051
.ofuncs = &(struct nouveau_ofuncs) {
51-
.ctor = _nouveau_engctx_ctor,
52-
.dtor = _nouveau_engctx_dtor,
53-
.init = _nouveau_engctx_init,
54-
.fini = _nouveau_engctx_fini,
55-
.rd32 = _nouveau_engctx_rd32,
56-
.wr32 = _nouveau_engctx_wr32,
52+
.ctor = _nouveau_falcon_context_ctor,
53+
.dtor = _nouveau_falcon_context_dtor,
54+
.init = _nouveau_falcon_context_init,
55+
.fini = _nouveau_falcon_context_fini,
56+
.rd32 = _nouveau_falcon_context_rd32,
57+
.wr32 = _nouveau_falcon_context_wr32,
5758
},
5859
};
5960

6061
/*******************************************************************************
61-
* BSP engine/subdev functions
62+
* PBSP engine/subdev functions
6263
******************************************************************************/
6364

65+
static int
66+
nv98_bsp_init(struct nouveau_object *object)
67+
{
68+
struct nv98_bsp_priv *priv = (void *)object;
69+
int ret;
70+
71+
ret = nouveau_falcon_init(&priv->base);
72+
if (ret)
73+
return ret;
74+
75+
nv_wr32(priv, 0x084010, 0x0000ffd2);
76+
nv_wr32(priv, 0x08401c, 0x0000fff2);
77+
return 0;
78+
}
79+
6480
static int
6581
nv98_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
6682
struct nouveau_oclass *oclass, void *data, u32 size,
@@ -69,7 +85,7 @@ nv98_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
6985
struct nv98_bsp_priv *priv;
7086
int ret;
7187

72-
ret = nouveau_engine_create(parent, engine, oclass, true,
88+
ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,
7389
"PBSP", "bsp", &priv);
7490
*pobject = nv_object(priv);
7591
if (ret)
@@ -86,8 +102,10 @@ nv98_bsp_oclass = {
86102
.handle = NV_ENGINE(BSP, 0x98),
87103
.ofuncs = &(struct nouveau_ofuncs) {
88104
.ctor = nv98_bsp_ctor,
89-
.dtor = _nouveau_engine_dtor,
90-
.init = _nouveau_engine_init,
91-
.fini = _nouveau_engine_fini,
105+
.dtor = _nouveau_falcon_dtor,
106+
.init = nv98_bsp_init,
107+
.fini = _nouveau_falcon_fini,
108+
.rd32 = _nouveau_falcon_rd32,
109+
.wr32 = _nouveau_falcon_wr32,
92110
},
93111
};

‎drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -49,18 +49,23 @@ int
4949
nv50_dac_sense(struct nv50_disp_priv *priv, int or, u32 loadval)
5050
{
5151
const u32 doff = (or * 0x800);
52-
int load = -EINVAL;
52+
5353
nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80150000);
5454
nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
55+
5556
nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval);
5657
mdelay(9);
5758
udelay(500);
58-
nv_wr32(priv, 0x61a00c + doff, 0x80000000);
59-
load = (nv_rd32(priv, 0x61a00c + doff) & 0x38000000) >> 27;
60-
nv_wr32(priv, 0x61a00c + doff, 0x00000000);
59+
loadval = nv_mask(priv, 0x61a00c + doff, 0xffffffff, 0x00000000);
60+
6161
nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80550000);
6262
nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
63-
return load;
63+
64+
nv_debug(priv, "DAC%d sense: 0x%08x\n", or, loadval);
65+
if (!(loadval & 0x80000000))
66+
return -ETIMEDOUT;
67+
68+
return (loadval & 0x38000000) >> 27;
6469
}
6570

6671
int

‎drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -628,7 +628,7 @@ nv50_disp_base_init(struct nouveau_object *object)
628628
}
629629

630630
/* ... PIOR caps */
631-
for (i = 0; i < 3; i++) {
631+
for (i = 0; i < priv->pior.nr; i++) {
632632
tmp = nv_rd32(priv, 0x61e000 + (i * 0x800));
633633
nv_wr32(priv, 0x6101f0 + (i * 0x04), tmp);
634634
}
@@ -834,30 +834,30 @@ exec_script(struct nv50_disp_priv *priv, int head, int id)
834834
u8 ver, hdr, cnt, len;
835835
u16 data;
836836
u32 ctrl = 0x00000000;
837+
u32 reg;
837838
int i;
838839

839840
/* DAC */
840-
for (i = 0; !(ctrl & (1 << head)) && i < 3; i++)
841+
for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++)
841842
ctrl = nv_rd32(priv, 0x610b5c + (i * 8));
842843

843844
/* SOR */
844845
if (!(ctrl & (1 << head))) {
845846
if (nv_device(priv)->chipset < 0x90 ||
846847
nv_device(priv)->chipset == 0x92 ||
847848
nv_device(priv)->chipset == 0xa0) {
848-
for (i = 0; !(ctrl & (1 << head)) && i < 2; i++)
849-
ctrl = nv_rd32(priv, 0x610b74 + (i * 8));
850-
i += 4;
849+
reg = 0x610b74;
851850
} else {
852-
for (i = 0; !(ctrl & (1 << head)) && i < 4; i++)
853-
ctrl = nv_rd32(priv, 0x610798 + (i * 8));
854-
i += 4;
851+
reg = 0x610798;
855852
}
853+
for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++)
854+
ctrl = nv_rd32(priv, reg + (i * 8));
855+
i += 4;
856856
}
857857

858858
/* PIOR */
859859
if (!(ctrl & (1 << head))) {
860-
for (i = 0; !(ctrl & (1 << head)) && i < 3; i++)
860+
for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++)
861861
ctrl = nv_rd32(priv, 0x610b84 + (i * 8));
862862
i += 8;
863863
}
@@ -893,30 +893,30 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk,
893893
u8 ver, hdr, cnt, len;
894894
u32 ctrl = 0x00000000;
895895
u32 data, conf = ~0;
896+
u32 reg;
896897
int i;
897898

898899
/* DAC */
899-
for (i = 0; !(ctrl & (1 << head)) && i < 3; i++)
900+
for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++)
900901
ctrl = nv_rd32(priv, 0x610b58 + (i * 8));
901902

902903
/* SOR */
903904
if (!(ctrl & (1 << head))) {
904905
if (nv_device(priv)->chipset < 0x90 ||
905906
nv_device(priv)->chipset == 0x92 ||
906907
nv_device(priv)->chipset == 0xa0) {
907-
for (i = 0; !(ctrl & (1 << head)) && i < 2; i++)
908-
ctrl = nv_rd32(priv, 0x610b70 + (i * 8));
909-
i += 4;
908+
reg = 0x610b70;
910909
} else {
911-
for (i = 0; !(ctrl & (1 << head)) && i < 4; i++)
912-
ctrl = nv_rd32(priv, 0x610794 + (i * 8));
913-
i += 4;
910+
reg = 0x610794;
914911
}
912+
for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++)
913+
ctrl = nv_rd32(priv, reg + (i * 8));
914+
i += 4;
915915
}
916916

917917
/* PIOR */
918918
if (!(ctrl & (1 << head))) {
919-
for (i = 0; !(ctrl & (1 << head)) && i < 3; i++)
919+
for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++)
920920
ctrl = nv_rd32(priv, 0x610b80 + (i * 8));
921921
i += 8;
922922
}

‎drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,6 @@
2626
#include <core/engctx.h>
2727
#include <core/ramht.h>
2828
#include <core/class.h>
29-
#include <core/math.h>
3029

3130
#include <subdev/timer.h>
3231
#include <subdev/bar.h>
@@ -278,7 +277,7 @@ nv50_fifo_chan_ctor_ind(struct nouveau_object *parent,
278277
return ret;
279278

280279
ioffset = args->ioffset;
281-
ilength = log2i(args->ilength / 8);
280+
ilength = order_base_2(args->ilength / 8);
282281

283282
nv_wo32(base->ramfc, 0x3c, 0x403f6078);
284283
nv_wo32(base->ramfc, 0x44, 0x01003fff);

‎drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,6 @@
2828
#include <core/ramht.h>
2929
#include <core/event.h>
3030
#include <core/class.h>
31-
#include <core/math.h>
3231

3332
#include <subdev/timer.h>
3433
#include <subdev/bar.h>
@@ -57,6 +56,7 @@ nv84_fifo_context_attach(struct nouveau_object *parent,
5756
case NVDEV_ENGINE_SW : return 0;
5857
case NVDEV_ENGINE_GR : addr = 0x0020; break;
5958
case NVDEV_ENGINE_VP : addr = 0x0040; break;
59+
case NVDEV_ENGINE_PPP :
6060
case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
6161
case NVDEV_ENGINE_BSP : addr = 0x0080; break;
6262
case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
@@ -92,6 +92,7 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
9292
case NVDEV_ENGINE_SW : return 0;
9393
case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break;
9494
case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break;
95+
case NVDEV_ENGINE_PPP :
9596
case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
9697
case NVDEV_ENGINE_BSP : engn = 5; addr = 0x0080; break;
9798
case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
@@ -258,7 +259,7 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
258259
nv_parent(chan)->object_detach = nv50_fifo_object_detach;
259260

260261
ioffset = args->ioffset;
261-
ilength = log2i(args->ilength / 8);
262+
ilength = order_base_2(args->ilength / 8);
262263

263264
nv_wo32(base->ramfc, 0x3c, 0x403f6078);
264265
nv_wo32(base->ramfc, 0x44, 0x01003fff);

‎drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,6 @@
2929
#include <core/engctx.h>
3030
#include <core/event.h>
3131
#include <core/class.h>
32-
#include <core/math.h>
3332
#include <core/enum.h>
3433

3534
#include <subdev/timer.h>
@@ -200,7 +199,7 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent,
200199

201200
usermem = chan->base.chid * 0x1000;
202201
ioffset = args->ioffset;
203-
ilength = log2i(args->ilength / 8);
202+
ilength = order_base_2(args->ilength / 8);
204203

205204
for (i = 0; i < 0x1000; i += 4)
206205
nv_wo32(priv->user.mem, usermem + i, 0x00000000);

‎drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,6 @@
2929
#include <core/engctx.h>
3030
#include <core/event.h>
3131
#include <core/class.h>
32-
#include <core/math.h>
3332
#include <core/enum.h>
3433

3534
#include <subdev/timer.h>
@@ -240,7 +239,7 @@ nve0_fifo_chan_ctor(struct nouveau_object *parent,
240239

241240
usermem = chan->base.chid * 0x200;
242241
ioffset = args->ioffset;
243-
ilength = log2i(args->ilength / 8);
242+
ilength = order_base_2(args->ilength / 8);
244243

245244
for (i = 0; i < 0x200; i += 4)
246245
nv_wo32(priv->user.mem, usermem + i, 0x00000000);

‎drivers/gpu/drm/nouveau/core/engine/graph/nv40.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,9 @@
11
#ifndef __NV40_GRAPH_H__
22
#define __NV40_GRAPH_H__
33

4+
#include <core/device.h>
5+
#include <core/gpuobj.h>
6+
47
/* returns 1 if device is one of the nv4x using the 0x4497 object class,
58
* helpful to determine a number of other hardware features
69
*/

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