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| 1 | +Renesas R-Car CAN FD controller Device Tree Bindings |
| 2 | +---------------------------------------------------- |
| 3 | + |
| 4 | +Required properties: |
| 5 | +- compatible: Must contain one or more of the following: |
| 6 | + - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller. |
| 7 | + - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller. |
| 8 | + |
| 9 | + When compatible with the generic version, nodes must list the |
| 10 | + SoC-specific version corresponding to the platform first, followed by the |
| 11 | + family-specific and/or generic versions. |
| 12 | + |
| 13 | +- reg: physical base address and size of the R-Car CAN FD register map. |
| 14 | +- interrupts: interrupt specifier for the Global & Channel interrupts |
| 15 | +- clocks: phandles and clock specifiers for 3 clock inputs. |
| 16 | +- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk". |
| 17 | +- pinctrl-0: pin control group to be used for this controller. |
| 18 | +- pinctrl-names: must be "default". |
| 19 | + |
| 20 | +Required child nodes: |
| 21 | +The controller supports two channels and each is represented as a child node. |
| 22 | +The name of the child nodes are "channel0" and "channel1" respectively. Each |
| 23 | +child node supports the "status" property only, which is used to |
| 24 | +enable/disable the respective channel. |
| 25 | + |
| 26 | +Required properties for "renesas,r8a7795-canfd" compatible: |
| 27 | +In R8A7795 SoC, canfd clock is a div6 clock and can be used by both CAN |
| 28 | +and CAN FD controller at the same time. It needs to be scaled to maximum |
| 29 | +frequency if any of these controllers use it. This is done using the |
| 30 | +below properties. |
| 31 | + |
| 32 | +- assigned-clocks: phandle of canfd clock. |
| 33 | +- assigned-clock-rates: maximum frequency of this clock. |
| 34 | + |
| 35 | +Example |
| 36 | +------- |
| 37 | + |
| 38 | +SoC common .dtsi file: |
| 39 | + |
| 40 | + canfd: can@e66c0000 { |
| 41 | + compatible = "renesas,r8a7795-canfd", |
| 42 | + "renesas,rcar-gen3-canfd"; |
| 43 | + reg = <0 0xe66c0000 0 0x8000>; |
| 44 | + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, |
| 45 | + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| 46 | + clocks = <&cpg CPG_MOD 914>, |
| 47 | + <&cpg CPG_CORE R8A7795_CLK_CANFD>, |
| 48 | + <&can_clk>; |
| 49 | + clock-names = "fck", "canfd", "can_clk"; |
| 50 | + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; |
| 51 | + assigned-clock-rates = <40000000>; |
| 52 | + power-domains = <&cpg>; |
| 53 | + status = "disabled"; |
| 54 | + |
| 55 | + channel0 { |
| 56 | + status = "disabled"; |
| 57 | + }; |
| 58 | + |
| 59 | + channel1 { |
| 60 | + status = "disabled"; |
| 61 | + }; |
| 62 | + }; |
| 63 | + |
| 64 | +Board specific .dts file: |
| 65 | + |
| 66 | +E.g. below enables Channel 1 alone in the board. |
| 67 | + |
| 68 | +&canfd { |
| 69 | + pinctrl-0 = <&canfd1_pins>; |
| 70 | + pinctrl-names = "default"; |
| 71 | + status = "okay"; |
| 72 | + |
| 73 | + channel1 { |
| 74 | + status = "okay"; |
| 75 | + }; |
| 76 | +}; |
| 77 | + |
| 78 | +E.g. below enables Channel 0 alone in the board using External clock |
| 79 | +as fCAN clock. |
| 80 | + |
| 81 | +&canfd { |
| 82 | + pinctrl-0 = <&canfd0_pins &can_clk_pins>; |
| 83 | + pinctrl-names = "default"; |
| 84 | + status = "okay"; |
| 85 | + |
| 86 | + channel0 { |
| 87 | + status = "okay"; |
| 88 | + }; |
| 89 | +}; |
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