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Pavana Sharmadavem330
Pavana Sharma
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davem330
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net: dsa: mv88e6xxx: add support for mv88e6393x family
The Marvell 88E6393X device is a single-chip integration of a 11-port Ethernet switch with eight integrated Gigabit Ethernet (GbE) transceivers and three 10-Gigabit interfaces. This patch adds functionalities specific to mv88e6393x family (88E6393X, 88E6193X and 88E6191X). The main differences between previous devices and this one are: - port 0 can be a SERDES port - all SERDESes are one-lane, eg. no XAUI nor RXAUI - on the other hand the SERDESes can do USXGMII, 10GBASER and 5GBASER (on 6191X only one SERDES is capable of more than 1g; USXGMII is not yet supported with this change) - Port Policy CTL register is changed to Port Policy MGMT CTL register, via which several more registers can be accessed indirectly - egress monitor port is configured differently - ingress monitor/CPU/mirror ports are configured differently and can be configured per port (ie. each port can have different ingress monitor port, for example) - port speed AltBit works differently than previously - PHY registers can be also accessed via MDIO address 0x18 and 0x19 (on previous devices they could be accessed only via Global 2 offsets 0x18 and 0x19, which means two indirections; this feature is not yet leveraged with thiis commit) Co-developed-by: Ashkan Boldaji <[email protected]> Signed-off-by: Ashkan Boldaji <[email protected]> Signed-off-by: Pavana Sharma <[email protected]> Co-developed-by: Marek Behún <[email protected]> Signed-off-by: Marek Behún <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/dsa/mv88e6xxx/chip.c

Lines changed: 155 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -635,6 +635,29 @@ static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
635635
mv88e6390_phylink_validate(chip, port, mask, state);
636636
}
637637

638+
static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
639+
unsigned long *mask,
640+
struct phylink_link_state *state)
641+
{
642+
if (port == 0 || port == 9 || port == 10) {
643+
phylink_set(mask, 10000baseT_Full);
644+
phylink_set(mask, 10000baseKR_Full);
645+
phylink_set(mask, 10000baseCR_Full);
646+
phylink_set(mask, 10000baseSR_Full);
647+
phylink_set(mask, 10000baseLR_Full);
648+
phylink_set(mask, 10000baseLRM_Full);
649+
phylink_set(mask, 10000baseER_Full);
650+
phylink_set(mask, 5000baseT_Full);
651+
phylink_set(mask, 2500baseX_Full);
652+
phylink_set(mask, 2500baseT_Full);
653+
}
654+
655+
phylink_set(mask, 1000baseT_Full);
656+
phylink_set(mask, 1000baseX_Full);
657+
658+
mv88e6065_phylink_validate(chip, port, mask, state);
659+
}
660+
638661
static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
639662
unsigned long *supported,
640663
struct phylink_link_state *state)
@@ -4589,6 +4612,69 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
45894612
.phylink_validate = mv88e6390x_phylink_validate,
45904613
};
45914614

4615+
static const struct mv88e6xxx_ops mv88e6393x_ops = {
4616+
/* MV88E6XXX_FAMILY_6393 */
4617+
.setup_errata = mv88e6393x_serdes_setup_errata,
4618+
.irl_init_all = mv88e6390_g2_irl_init_all,
4619+
.get_eeprom = mv88e6xxx_g2_get_eeprom8,
4620+
.set_eeprom = mv88e6xxx_g2_set_eeprom8,
4621+
.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4622+
.phy_read = mv88e6xxx_g2_smi_phy_read,
4623+
.phy_write = mv88e6xxx_g2_smi_phy_write,
4624+
.port_set_link = mv88e6xxx_port_set_link,
4625+
.port_sync_link = mv88e6xxx_port_sync_link,
4626+
.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4627+
.port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
4628+
.port_max_speed_mode = mv88e6393x_port_max_speed_mode,
4629+
.port_tag_remap = mv88e6390_port_tag_remap,
4630+
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4631+
.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4632+
.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4633+
.port_set_ether_type = mv88e6393x_port_set_ether_type,
4634+
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4635+
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4636+
.port_pause_limit = mv88e6390_port_pause_limit,
4637+
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4638+
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4639+
.port_get_cmode = mv88e6352_port_get_cmode,
4640+
.port_set_cmode = mv88e6393x_port_set_cmode,
4641+
.port_setup_message_port = mv88e6xxx_setup_message_port,
4642+
.port_set_upstream_port = mv88e6393x_port_set_upstream_port,
4643+
.stats_snapshot = mv88e6390_g1_stats_snapshot,
4644+
.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4645+
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
4646+
.stats_get_strings = mv88e6320_stats_get_strings,
4647+
.stats_get_stats = mv88e6390_stats_get_stats,
4648+
/* .set_cpu_port is missing because this family does not support a global
4649+
* CPU port, only per port CPU port which is set via
4650+
* .port_set_upstream_port method.
4651+
*/
4652+
.set_egress_port = mv88e6393x_set_egress_port,
4653+
.watchdog_ops = &mv88e6390_watchdog_ops,
4654+
.mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
4655+
.pot_clear = mv88e6xxx_g2_pot_clear,
4656+
.reset = mv88e6352_g1_reset,
4657+
.rmu_disable = mv88e6390_g1_rmu_disable,
4658+
.atu_get_hash = mv88e6165_g1_atu_get_hash,
4659+
.atu_set_hash = mv88e6165_g1_atu_set_hash,
4660+
.vtu_getnext = mv88e6390_g1_vtu_getnext,
4661+
.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4662+
.serdes_power = mv88e6393x_serdes_power,
4663+
.serdes_get_lane = mv88e6393x_serdes_get_lane,
4664+
.serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state,
4665+
.serdes_pcs_config = mv88e6390_serdes_pcs_config,
4666+
.serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4667+
.serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4668+
.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4669+
.serdes_irq_enable = mv88e6393x_serdes_irq_enable,
4670+
.serdes_irq_status = mv88e6393x_serdes_irq_status,
4671+
/* TODO: serdes stats */
4672+
.gpio_ops = &mv88e6352_gpio_ops,
4673+
.avb_ops = &mv88e6390_avb_ops,
4674+
.ptp_ops = &mv88e6352_ptp_ops,
4675+
.phylink_validate = mv88e6393x_phylink_validate,
4676+
};
4677+
45924678
static const struct mv88e6xxx_info mv88e6xxx_table[] = {
45934679
[MV88E6085] = {
45944680
.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
@@ -4960,6 +5046,52 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
49605046
.ops = &mv88e6191_ops,
49615047
},
49625048

5049+
[MV88E6191X] = {
5050+
.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5051+
.family = MV88E6XXX_FAMILY_6393,
5052+
.name = "Marvell 88E6191X",
5053+
.num_databases = 4096,
5054+
.num_ports = 11, /* 10 + Z80 */
5055+
.num_internal_phys = 9,
5056+
.max_vid = 8191,
5057+
.port_base_addr = 0x0,
5058+
.phy_base_addr = 0x0,
5059+
.global1_addr = 0x1b,
5060+
.global2_addr = 0x1c,
5061+
.age_time_coeff = 3750,
5062+
.g1_irqs = 10,
5063+
.g2_irqs = 14,
5064+
.atu_move_port_mask = 0x1f,
5065+
.pvt = true,
5066+
.multi_chip = true,
5067+
.tag_protocol = DSA_TAG_PROTO_DSA,
5068+
.ptp_support = true,
5069+
.ops = &mv88e6393x_ops,
5070+
},
5071+
5072+
[MV88E6193X] = {
5073+
.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5074+
.family = MV88E6XXX_FAMILY_6393,
5075+
.name = "Marvell 88E6193X",
5076+
.num_databases = 4096,
5077+
.num_ports = 11, /* 10 + Z80 */
5078+
.num_internal_phys = 9,
5079+
.max_vid = 8191,
5080+
.port_base_addr = 0x0,
5081+
.phy_base_addr = 0x0,
5082+
.global1_addr = 0x1b,
5083+
.global2_addr = 0x1c,
5084+
.age_time_coeff = 3750,
5085+
.g1_irqs = 10,
5086+
.g2_irqs = 14,
5087+
.atu_move_port_mask = 0x1f,
5088+
.pvt = true,
5089+
.multi_chip = true,
5090+
.tag_protocol = DSA_TAG_PROTO_DSA,
5091+
.ptp_support = true,
5092+
.ops = &mv88e6393x_ops,
5093+
},
5094+
49635095
[MV88E6220] = {
49645096
.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
49655097
.family = MV88E6XXX_FAMILY_6250,
@@ -5250,6 +5382,29 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
52505382
.ptp_support = true,
52515383
.ops = &mv88e6390x_ops,
52525384
},
5385+
5386+
[MV88E6393X] = {
5387+
.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
5388+
.family = MV88E6XXX_FAMILY_6393,
5389+
.name = "Marvell 88E6393X",
5390+
.num_databases = 4096,
5391+
.num_ports = 11, /* 10 + Z80 */
5392+
.num_internal_phys = 9,
5393+
.max_vid = 8191,
5394+
.port_base_addr = 0x0,
5395+
.phy_base_addr = 0x0,
5396+
.global1_addr = 0x1b,
5397+
.global2_addr = 0x1c,
5398+
.age_time_coeff = 3750,
5399+
.g1_irqs = 10,
5400+
.g2_irqs = 14,
5401+
.atu_move_port_mask = 0x1f,
5402+
.pvt = true,
5403+
.multi_chip = true,
5404+
.tag_protocol = DSA_TAG_PROTO_DSA,
5405+
.ptp_support = true,
5406+
.ops = &mv88e6393x_ops,
5407+
},
52535408
};
52545409

52555410
static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)

‎drivers/net/dsa/mv88e6xxx/chip.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,8 @@ enum mv88e6xxx_model {
6363
MV88E6190,
6464
MV88E6190X,
6565
MV88E6191,
66+
MV88E6191X,
67+
MV88E6193X,
6668
MV88E6220,
6769
MV88E6240,
6870
MV88E6250,
@@ -75,6 +77,7 @@ enum mv88e6xxx_model {
7577
MV88E6352,
7678
MV88E6390,
7779
MV88E6390X,
80+
MV88E6393X,
7881
};
7982

8083
enum mv88e6xxx_family {
@@ -90,6 +93,7 @@ enum mv88e6xxx_family {
9093
MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
9194
MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
9295
MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
96+
MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6393X */
9397
};
9498

9599
struct mv88e6xxx_ops;

‎drivers/net/dsa/mv88e6xxx/global1.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@
2222
#define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000
2323
#define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000
2424
#define MV88E6XXX_G1_STS_INIT_READY 0x0800
25+
#define MV88E6393X_G1_STS_IRQ_DEVICE_2 9
2526
#define MV88E6XXX_G1_STS_IRQ_AVB 8
2627
#define MV88E6XXX_G1_STS_IRQ_DEVICE 7
2728
#define MV88E6XXX_G1_STS_IRQ_STATS 6
@@ -59,6 +60,7 @@
5960
#define MV88E6185_G1_CTL1_SCHED_PRIO 0x0800
6061
#define MV88E6185_G1_CTL1_MAX_FRAME_1632 0x0400
6162
#define MV88E6185_G1_CTL1_RELOAD_EEPROM 0x0200
63+
#define MV88E6393X_G1_CTL1_DEVICE2_EN 0x0200
6264
#define MV88E6XXX_G1_CTL1_DEVICE_EN 0x0080
6365
#define MV88E6XXX_G1_CTL1_STATS_DONE_EN 0x0040
6466
#define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN 0x0020

‎drivers/net/dsa/mv88e6xxx/global2.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,9 +38,15 @@
3838
/* Offset 0x02: MGMT Enable Register 2x */
3939
#define MV88E6XXX_G2_MGMT_EN_2X 0x02
4040

41+
/* Offset 0x02: MAC LINK change IRQ Register for MV88E6393X */
42+
#define MV88E6393X_G2_MACLINK_INT_SRC 0x02
43+
4144
/* Offset 0x03: MGMT Enable Register 0x */
4245
#define MV88E6XXX_G2_MGMT_EN_0X 0x03
4346

47+
/* Offset 0x03: MAC LINK change IRQ Mask Register for MV88E6393X */
48+
#define MV88E6393X_G2_MACLINK_INT_MASK 0x03
49+
4450
/* Offset 0x04: Flow Control Delay Register */
4551
#define MV88E6XXX_G2_FLOW_CTL 0x04
4652

@@ -52,6 +58,8 @@
5258
#define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080
5359
#define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008
5460

61+
#define MV88E6393X_G2_EGRESS_MONITOR_DEST 0x05
62+
5563
/* Offset 0x06: Device Mapping Table Register */
5664
#define MV88E6XXX_G2_DEVICE_MAPPING 0x06
5765
#define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x8000

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