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Shubhrajyoti Dattasuryasaimadhu
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EDAC/synopsys: Read the error count from the correct register
Currently, the error count is read wrongly from the status register. Read the count from the proper error count register (ERRCNT). [ bp: Massage. ] Fixes: b500b4a ("EDAC, synopsys: Add ECC support for ZynqMP DDR controller") Signed-off-by: Shubhrajyoti Datta <[email protected]> Signed-off-by: Borislav Petkov <[email protected]> Acked-by: Michal Simek <[email protected]> Cc: <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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drivers/edac/synopsys_edac.c

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -164,6 +164,11 @@
164164
#define ECC_STAT_CECNT_SHIFT 8
165165
#define ECC_STAT_BITNUM_MASK 0x7F
166166

167+
/* ECC error count register definitions */
168+
#define ECC_ERRCNT_UECNT_MASK 0xFFFF0000
169+
#define ECC_ERRCNT_UECNT_SHIFT 16
170+
#define ECC_ERRCNT_CECNT_MASK 0xFFFF
171+
167172
/* DDR QOS Interrupt register definitions */
168173
#define DDR_QOS_IRQ_STAT_OFST 0x20200
169174
#define DDR_QOSUE_MASK 0x4
@@ -423,15 +428,16 @@ static int zynqmp_get_error_info(struct synps_edac_priv *priv)
423428
base = priv->baseaddr;
424429
p = &priv->stat;
425430

431+
regval = readl(base + ECC_ERRCNT_OFST);
432+
p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK;
433+
p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT;
434+
if (!p->ce_cnt)
435+
goto ue_err;
436+
426437
regval = readl(base + ECC_STAT_OFST);
427438
if (!regval)
428439
return 1;
429440

430-
p->ce_cnt = (regval & ECC_STAT_CECNT_MASK) >> ECC_STAT_CECNT_SHIFT;
431-
p->ue_cnt = (regval & ECC_STAT_UECNT_MASK) >> ECC_STAT_UECNT_SHIFT;
432-
if (!p->ce_cnt)
433-
goto ue_err;
434-
435441
p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK);
436442

437443
regval = readl(base + ECC_CEADDR0_OFST);

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