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matthew-gerlachgregkh
matthew-gerlach
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tty: serial: 8250: add DFL bus driver for Altera 16550.
Add a Device Feature List (DFL) bus driver for the Altera 16550 implementation of UART. Signed-off-by: Matthew Gerlach <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Marco Pagani <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
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‎drivers/tty/serial/8250/8250_dfl.c

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for FPGA UART
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*
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* Copyright (C) 2022 Intel Corporation.
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*
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* Authors:
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* Ananda Ravuri <[email protected]>
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* Matthew Gerlach <[email protected]>
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*/
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#include <linux/bitfield.h>
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#include <linux/device.h>
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#include <linux/dfl.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/types.h>
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#include <linux/serial.h>
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#include <linux/serial_8250.h>
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#define DFHv1_PARAM_ID_CLK_FRQ 0x2
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#define DFHv1_PARAM_ID_FIFO_LEN 0x3
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#define DFHv1_PARAM_ID_REG_LAYOUT 0x4
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#define DFHv1_PARAM_REG_LAYOUT_WIDTH GENMASK_ULL(63, 32)
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#define DFHv1_PARAM_REG_LAYOUT_SHIFT GENMASK_ULL(31, 0)
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struct dfl_uart {
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int line;
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};
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static int dfh_get_u64_param_val(struct dfl_device *dfl_dev, int param_id, u64 *pval)
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{
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size_t psize;
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u64 *p;
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p = dfh_find_param(dfl_dev, param_id, &psize);
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if (IS_ERR(p))
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return PTR_ERR(p);
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if (psize != sizeof(*pval))
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return -EINVAL;
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*pval = *p;
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return 0;
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}
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static int dfl_uart_get_params(struct dfl_device *dfl_dev, struct uart_8250_port *uart)
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{
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struct device *dev = &dfl_dev->dev;
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u64 fifo_len, clk_freq, reg_layout;
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u32 reg_width;
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int ret;
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ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_CLK_FRQ, &clk_freq);
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if (ret)
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return dev_err_probe(dev, ret, "missing CLK_FRQ param\n");
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uart->port.uartclk = clk_freq;
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ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_FIFO_LEN, &fifo_len);
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if (ret)
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return dev_err_probe(dev, ret, "missing FIFO_LEN param\n");
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switch (fifo_len) {
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case 32:
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uart->port.type = PORT_ALTR_16550_F32;
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break;
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case 64:
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uart->port.type = PORT_ALTR_16550_F64;
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break;
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case 128:
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uart->port.type = PORT_ALTR_16550_F128;
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break;
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default:
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return dev_err_probe(dev, -EINVAL, "unsupported FIFO_LEN %llu\n", fifo_len);
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}
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ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_REG_LAYOUT, &reg_layout);
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if (ret)
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return dev_err_probe(dev, ret, "missing REG_LAYOUT param\n");
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uart->port.regshift = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_SHIFT, reg_layout);
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reg_width = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_WIDTH, reg_layout);
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switch (reg_width) {
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case 4:
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uart->port.iotype = UPIO_MEM32;
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break;
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case 2:
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uart->port.iotype = UPIO_MEM16;
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break;
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default:
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return dev_err_probe(dev, -EINVAL, "unsupported reg-width %u\n", reg_width);
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}
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return 0;
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}
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static int dfl_uart_probe(struct dfl_device *dfl_dev)
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{
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struct device *dev = &dfl_dev->dev;
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struct uart_8250_port uart = { };
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struct dfl_uart *dfluart;
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int ret;
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uart.port.flags = UPF_IOREMAP;
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uart.port.mapbase = dfl_dev->mmio_res.start;
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uart.port.mapsize = resource_size(&dfl_dev->mmio_res);
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ret = dfl_uart_get_params(dfl_dev, &uart);
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if (ret < 0)
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return dev_err_probe(dev, ret, "failed uart feature walk\n");
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if (dfl_dev->num_irqs == 1)
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uart.port.irq = dfl_dev->irqs[0];
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dfluart = devm_kzalloc(dev, sizeof(*dfluart), GFP_KERNEL);
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if (!dfluart)
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return -ENOMEM;
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dfluart->line = serial8250_register_8250_port(&uart);
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if (dfluart->line < 0)
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return dev_err_probe(dev, dfluart->line, "unable to register 8250 port.\n");
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dev_set_drvdata(dev, dfluart);
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return 0;
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}
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static void dfl_uart_remove(struct dfl_device *dfl_dev)
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{
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struct dfl_uart *dfluart = dev_get_drvdata(&dfl_dev->dev);
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serial8250_unregister_port(dfluart->line);
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}
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#define FME_FEATURE_ID_UART 0x24
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static const struct dfl_device_id dfl_uart_ids[] = {
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{ FME_ID, FME_FEATURE_ID_UART },
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{ }
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};
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MODULE_DEVICE_TABLE(dfl, dfl_uart_ids);
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static struct dfl_driver dfl_uart_driver = {
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.drv = {
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.name = "dfl-uart",
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},
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.id_table = dfl_uart_ids,
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.probe = dfl_uart_probe,
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.remove = dfl_uart_remove,
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};
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module_dfl_driver(dfl_uart_driver);
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MODULE_DESCRIPTION("DFL Intel UART driver");
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MODULE_AUTHOR("Intel Corporation");
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MODULE_LICENSE("GPL");

‎drivers/tty/serial/8250/Kconfig

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erratum for Freescale 16550 UARTs in the 8250 driver. It also
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enables support for ACPI enumeration.
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config SERIAL_8250_DFL
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tristate "DFL bus driver for Altera 16550 UART"
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depends on SERIAL_8250 && FPGA_DFL
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help
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This option enables support for a Device Feature List (DFL) bus
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driver for the Altera 16550 UART. One or more Altera 16550 UARTs
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can be instantiated in a FPGA and then be discovered during
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enumeration of the DFL bus.
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To compile this driver as a module, chose M here: the
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module will be called 8250_dfl.
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config SERIAL_8250_DW
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tristate "Support for Synopsys DesignWare 8250 quirks"
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depends on SERIAL_8250

‎drivers/tty/serial/8250/Makefile

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@@ -28,6 +28,7 @@ obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o
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obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o
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obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o
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obj-$(CONFIG_SERIAL_8250_MEN_MCB) += 8250_men_mcb.o
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obj-$(CONFIG_SERIAL_8250_DFL) += 8250_dfl.o
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obj-$(CONFIG_SERIAL_8250_DW) += 8250_dw.o
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obj-$(CONFIG_SERIAL_8250_EM) += 8250_em.o
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obj-$(CONFIG_SERIAL_8250_IOC3) += 8250_ioc3.o

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