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xdarklightstorulf
xdarklight
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mmc: host: meson-mx-sdhc: new driver for the Amlogic Meson SDHC host
The SDHC MMC host controller on Amlogic SoCs provides an eMMC and MMC card interface with 1/4/8-bit bus width. It supports eMMC spec 4.4x/4.5x including HS200 (up to 100MHz clock). The public S805 datasheet [0] contains a short documentation about the registers. Unfortunately it does not describe how to use the registers to make the hardware work. Thus this driver is based on reading (and understanding) the Amlogic 3.10 GPL kernel code. Some hardware details are not easy to see. Jianxin Pan was kind enough to answer my questions: The hardware has built-in busy timeout support. The maximum timeout is 30 seconds. This is only documented in Amlogic's internal documentation. The controller only works with very specific clock configurations. The details are not part of the public datasheet. In my own words the supported configurations are: - 399.812kHz: clkin = 850MHz div = 2126 sd_rx_phase = 63 - 1MHz: clkin = 850MHz div = 850 sd_rx_phase = 55 - 5.986MHz: clkin = 850MHz div = 142 sd_rx_phase = 24 - 25MHz: clkin = 850MHz div = 34 sd_rx_phase = 15 - 47.222MHz: clkin = 850MHz div = 18 sd_rx_phase = 11/15 (SDR50/HS) - 53.125MHz: clkin = 850MHz div = 16 sd_rx_phase = (tuning) - 70.833MHz: clkin = 850MHz div = 12 sd_rx_phase = (tuning) - 85MHz: clkin = 850MHz div = 10 sd_rx_phase = (tuning) - 94.44MHz: clkin = 850MHz div = 9 sd_rx_phase = (tuning) - 106.25MHz: clkin = 850MHz div = 8 sd_rx_phase = (tuning) - 127.5MHz: clkin = 1275MHz div = 10 sd_rx_phase = (tuning) - 141.667MHz: clkin = 850MHz div = 6 sd_rx_phase = (tuning) - 159.375MHz: clkin = 1275MHz div = 8 sd_rx_phase = (tuning) - 212.5MHz: clkin = 1275MHz div = 6 sd_rx_phase = (tuning) - (sd_tx_phase is always 1, 94.44MHz is not listed in the datasheet but this is what the 3.10 BSP kernel on Odroid-C1 actually uses) NOTE: CMD23 support is disabled for now because it results in command timeouts and thus decreases read performance. Tested-by: Wei Wang <[email protected]> Tested-by: Xin Yin <[email protected]> Reviewed-by: Xin Yin <[email protected]> Tested-by: Anand Moon <[email protected]> Signed-off-by: Martin Blumenstingl <[email protected]> Reviewed-by: Jerome Brunet <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
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‎drivers/mmc/host/Kconfig

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@@ -405,6 +405,20 @@ config MMC_MESON_GX
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If you have a controller with this interface, say Y here.
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config MMC_MESON_MX_SDHC
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tristate "Amlogic Meson SDHC Host Controller support"
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depends on (ARM && ARCH_MESON) || COMPILE_TEST
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depends on COMMON_CLK
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depends on OF
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help
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This selects support for the SDHC Host Controller on
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Amlogic Meson6, Meson8, Meson8b and Meson8m2 SoCs.
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The controller supports the SD/SDIO Spec 3.x and eMMC Spec 4.5x
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with 1, 4, and 8 bit bus widths.
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If you have a controller with this interface, say Y or M here.
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If unsure, say N.
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config MMC_MESON_MX_SDIO
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tristate "Amlogic Meson6/Meson8/Meson8b SD/MMC Host Controller support"
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depends on ARCH_MESON || COMPILE_TEST

‎drivers/mmc/host/Makefile

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@@ -68,6 +68,7 @@ obj-$(CONFIG_MMC_VUB300) += vub300.o
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obj-$(CONFIG_MMC_USHC) += ushc.o
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obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o
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obj-$(CONFIG_MMC_MESON_GX) += meson-gx-mmc.o
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obj-$(CONFIG_MMC_MESON_MX_SDHC) += meson-mx-sdhc-clkc.o meson-mx-sdhc.o
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obj-$(CONFIG_MMC_MESON_MX_SDIO) += meson-mx-sdio.o
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obj-$(CONFIG_MMC_MOXART) += moxart-mmc.o
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obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o

‎drivers/mmc/host/meson-mx-sdhc-clkc.c

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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Amlogic Meson SDHC clock controller
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*
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* Copyright (C) 2020 Martin Blumenstingl <[email protected]>
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include "meson-mx-sdhc.h"
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#define MESON_SDHC_NUM_BUILTIN_CLKS 6
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struct meson_mx_sdhc_clkc {
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struct clk_mux src_sel;
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struct clk_divider div;
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struct clk_gate mod_clk_en;
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struct clk_gate tx_clk_en;
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struct clk_gate rx_clk_en;
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struct clk_gate sd_clk_en;
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};
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static const struct clk_parent_data meson_mx_sdhc_src_sel_parents[4] = {
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{ .fw_name = "clkin0" },
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{ .fw_name = "clkin1" },
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{ .fw_name = "clkin2" },
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{ .fw_name = "clkin3" },
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};
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static const struct clk_div_table meson_mx_sdhc_div_table[] = {
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{ .div = 6, .val = 5, },
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{ .div = 8, .val = 7, },
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{ .div = 9, .val = 8, },
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{ .div = 10, .val = 9, },
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{ .div = 12, .val = 11, },
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{ .div = 16, .val = 15, },
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{ .div = 18, .val = 17, },
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{ .div = 34, .val = 33, },
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{ .div = 142, .val = 141, },
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{ .div = 850, .val = 849, },
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{ .div = 2126, .val = 2125, },
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{ .div = 4096, .val = 4095, },
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{ /* sentinel */ }
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};
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static int meson_mx_sdhc_clk_hw_register(struct device *dev,
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const char *name_suffix,
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const struct clk_parent_data *parents,
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unsigned int num_parents,
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const struct clk_ops *ops,
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struct clk_hw *hw)
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{
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struct clk_init_data init = { 0 };
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char clk_name[32];
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snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dev),
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name_suffix);
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init.name = clk_name;
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init.ops = ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_data = parents;
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init.num_parents = num_parents;
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hw->init = &init;
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return devm_clk_hw_register(dev, hw);
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}
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static int meson_mx_sdhc_gate_clk_hw_register(struct device *dev,
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const char *name_suffix,
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struct clk_hw *parent,
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struct clk_hw *hw)
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{
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struct clk_parent_data parent_data = { .hw = parent };
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return meson_mx_sdhc_clk_hw_register(dev, name_suffix, &parent_data, 1,
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&clk_gate_ops, hw);
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}
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int meson_mx_sdhc_register_clkc(struct device *dev, void __iomem *base,
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struct clk_bulk_data *clk_bulk_data)
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{
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struct clk_parent_data div_parent = { 0 };
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struct meson_mx_sdhc_clkc *clkc_data;
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int ret;
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clkc_data = devm_kzalloc(dev, sizeof(*clkc_data), GFP_KERNEL);
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if (!clkc_data)
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return -ENOMEM;
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clkc_data->src_sel.reg = base + MESON_SDHC_CLKC;
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clkc_data->src_sel.mask = 0x3;
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clkc_data->src_sel.shift = 16;
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ret = meson_mx_sdhc_clk_hw_register(dev, "src_sel",
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meson_mx_sdhc_src_sel_parents, 4,
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&clk_mux_ops,
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&clkc_data->src_sel.hw);
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if (ret)
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return ret;
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clkc_data->div.reg = base + MESON_SDHC_CLKC;
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clkc_data->div.shift = 0;
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clkc_data->div.width = 12;
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clkc_data->div.table = meson_mx_sdhc_div_table;
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div_parent.hw = &clkc_data->src_sel.hw;
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ret = meson_mx_sdhc_clk_hw_register(dev, "div", &div_parent, 1,
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&clk_divider_ops,
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&clkc_data->div.hw);
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if (ret)
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return ret;
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clkc_data->mod_clk_en.reg = base + MESON_SDHC_CLKC;
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clkc_data->mod_clk_en.bit_idx = 15;
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ret = meson_mx_sdhc_gate_clk_hw_register(dev, "mod_clk_on",
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&clkc_data->div.hw,
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&clkc_data->mod_clk_en.hw);
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if (ret)
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return ret;
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clkc_data->tx_clk_en.reg = base + MESON_SDHC_CLKC;
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clkc_data->tx_clk_en.bit_idx = 14;
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ret = meson_mx_sdhc_gate_clk_hw_register(dev, "tx_clk_on",
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&clkc_data->div.hw,
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&clkc_data->tx_clk_en.hw);
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if (ret)
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return ret;
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clkc_data->rx_clk_en.reg = base + MESON_SDHC_CLKC;
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clkc_data->rx_clk_en.bit_idx = 13;
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ret = meson_mx_sdhc_gate_clk_hw_register(dev, "rx_clk_on",
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&clkc_data->div.hw,
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&clkc_data->rx_clk_en.hw);
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if (ret)
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return ret;
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clkc_data->sd_clk_en.reg = base + MESON_SDHC_CLKC;
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clkc_data->sd_clk_en.bit_idx = 12;
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ret = meson_mx_sdhc_gate_clk_hw_register(dev, "sd_clk_on",
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&clkc_data->div.hw,
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&clkc_data->sd_clk_en.hw);
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if (ret)
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return ret;
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/*
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* TODO: Replace clk_hw.clk with devm_clk_hw_get_clk() once that is
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* available.
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*/
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clk_bulk_data[0].clk = clkc_data->mod_clk_en.hw.clk;
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clk_bulk_data[1].clk = clkc_data->sd_clk_en.hw.clk;
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clk_bulk_data[2].clk = clkc_data->tx_clk_en.hw.clk;
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clk_bulk_data[3].clk = clkc_data->rx_clk_en.hw.clk;
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return 0;
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}

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