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29 | 29 | #include "mxsfb_drv.h"
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30 | 30 | #include "mxsfb_regs.h"
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31 | 31 |
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32 |
| -#define MXS_SET_ADDR 0x4 |
33 |
| -#define MXS_CLR_ADDR 0x8 |
34 |
| -#define MODULE_CLKGATE BIT(30) |
35 |
| -#define MODULE_SFTRST BIT(31) |
36 | 32 | /* 1 second delay should be plenty of time for block reset */
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37 | 33 | #define RESET_TIMEOUT 1000000
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38 | 34 |
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@@ -162,25 +158,25 @@ static int clear_poll_bit(void __iomem *addr, u32 mask)
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162 | 158 | {
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163 | 159 | u32 reg;
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164 | 160 |
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165 |
| - writel(mask, addr + MXS_CLR_ADDR); |
| 161 | + writel(mask, addr + REG_CLR); |
166 | 162 | return readl_poll_timeout(addr, reg, !(reg & mask), 0, RESET_TIMEOUT);
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167 | 163 | }
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168 | 164 |
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169 | 165 | static int mxsfb_reset_block(struct mxsfb_drm_private *mxsfb)
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170 | 166 | {
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171 | 167 | int ret;
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172 | 168 |
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173 |
| - ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, MODULE_SFTRST); |
| 169 | + ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_SFTRST); |
174 | 170 | if (ret)
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175 | 171 | return ret;
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176 | 172 |
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177 |
| - writel(MODULE_CLKGATE, mxsfb->base + LCDC_CTRL + MXS_CLR_ADDR); |
| 173 | + writel(CTRL_CLKGATE, mxsfb->base + LCDC_CTRL + REG_CLR); |
178 | 174 |
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179 |
| - ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, MODULE_SFTRST); |
| 175 | + ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_SFTRST); |
180 | 176 | if (ret)
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181 | 177 | return ret;
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182 | 178 |
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183 |
| - return clear_poll_bit(mxsfb->base + LCDC_CTRL, MODULE_CLKGATE); |
| 179 | + return clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_CLKGATE); |
184 | 180 | }
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185 | 181 |
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186 | 182 | static dma_addr_t mxsfb_get_fb_paddr(struct mxsfb_drm_private *mxsfb)
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