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net: stmmac: unify registers dumps methods
The stmmac driver have two methods for registers dumps: via ethtool and at init (if NETIF_MSG_HW is enabled). It is better to keep only one method, ethtool, since the other was ugly. This patch convert all dump_regs() function from "printing regs" to "fill the reg_space used by ethtool". Signed-off-by: Corentin Labbe <[email protected]> Acked-by: Giuseppe Cavallaro <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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9 files changed

+71
-121
lines changed

9 files changed

+71
-121
lines changed

‎drivers/net/ethernet/stmicro/stmmac/common.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -416,7 +416,7 @@ struct stmmac_dma_ops {
416416
/* Configure the AXI Bus Mode Register */
417417
void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
418418
/* Dump DMA registers */
419-
void (*dump_regs) (void __iomem *ioaddr);
419+
void (*dump_regs)(void __iomem *ioaddr, u32 *reg_space);
420420
/* Set tx/rx threshold in the csr6 register
421421
* An invalid value enables the store-and-forward mode */
422422
void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
@@ -456,7 +456,7 @@ struct stmmac_ops {
456456
/* Enable RX Queues */
457457
void (*rx_queue_enable)(struct mac_device_info *hw, u32 queue);
458458
/* Dump MAC registers */
459-
void (*dump_regs)(struct mac_device_info *hw);
459+
void (*dump_regs)(struct mac_device_info *hw, u32 *reg_space);
460460
/* Handle extra events on specific interrupts hw dependent */
461461
int (*host_irq_status)(struct mac_device_info *hw,
462462
struct stmmac_extra_stats *x);

‎drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -92,17 +92,13 @@ static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
9292
return !!(value & GMAC_CONTROL_IPC);
9393
}
9494

95-
static void dwmac1000_dump_regs(struct mac_device_info *hw)
95+
static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
9696
{
9797
void __iomem *ioaddr = hw->pcsr;
9898
int i;
99-
pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);
10099

101-
for (i = 0; i < 55; i++) {
102-
int offset = i * 4;
103-
pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
104-
offset, readl(ioaddr + offset));
105-
}
100+
for (i = 0; i < 55; i++)
101+
reg_space[i] = readl(ioaddr + i * 4);
106102
}
107103

108104
static void dwmac1000_set_umac_addr(struct mac_device_info *hw,

‎drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c

Lines changed: 6 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -201,18 +201,14 @@ static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode,
201201
writel(csr6, ioaddr + DMA_CONTROL);
202202
}
203203

204-
static void dwmac1000_dump_dma_regs(void __iomem *ioaddr)
204+
static void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
205205
{
206206
int i;
207-
pr_info(" DMA registers\n");
208-
for (i = 0; i < 22; i++) {
209-
if ((i < 9) || (i > 17)) {
210-
int offset = i * 4;
211-
pr_err("\t Reg No. %d (offset 0x%x): 0x%08x\n", i,
212-
(DMA_BUS_MODE + offset),
213-
readl(ioaddr + DMA_BUS_MODE + offset));
214-
}
215-
}
207+
208+
for (i = 0; i < 22; i++)
209+
if ((i < 9) || (i > 17))
210+
reg_space[DMA_BUS_MODE / 4 + i] =
211+
readl(ioaddr + DMA_BUS_MODE + i * 4);
216212
}
217213

218214
static void dwmac1000_get_hw_feature(void __iomem *ioaddr,

‎drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c

Lines changed: 10 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -40,28 +40,18 @@ static void dwmac100_core_init(struct mac_device_info *hw, int mtu)
4040
#endif
4141
}
4242

43-
static void dwmac100_dump_mac_regs(struct mac_device_info *hw)
43+
static void dwmac100_dump_mac_regs(struct mac_device_info *hw, u32 *reg_space)
4444
{
4545
void __iomem *ioaddr = hw->pcsr;
46-
pr_info("\t----------------------------------------------\n"
47-
"\t DWMAC 100 CSR (base addr = 0x%p)\n"
48-
"\t----------------------------------------------\n", ioaddr);
49-
pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
50-
readl(ioaddr + MAC_CONTROL));
51-
pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
52-
readl(ioaddr + MAC_ADDR_HIGH));
53-
pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
54-
readl(ioaddr + MAC_ADDR_LOW));
55-
pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
56-
MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
57-
pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
58-
MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
59-
pr_info("\tflow control (offset 0x%x): 0x%08x\n",
60-
MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
61-
pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
62-
readl(ioaddr + MAC_VLAN1));
63-
pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
64-
readl(ioaddr + MAC_VLAN2));
46+
47+
reg_space[MAC_CONTROL / 4] = readl(ioaddr + MAC_CONTROL);
48+
reg_space[MAC_ADDR_HIGH / 4] = readl(ioaddr + MAC_ADDR_HIGH);
49+
reg_space[MAC_ADDR_LOW / 4] = readl(ioaddr + MAC_ADDR_LOW);
50+
reg_space[MAC_HASH_HIGH / 4] = readl(ioaddr + MAC_HASH_HIGH);
51+
reg_space[MAC_HASH_LOW / 4] = readl(ioaddr + MAC_HASH_LOW);
52+
reg_space[MAC_FLOW_CTRL / 4] = readl(ioaddr + MAC_FLOW_CTRL);
53+
reg_space[MAC_VLAN1 / 4] = readl(ioaddr + MAC_VLAN1);
54+
reg_space[MAC_VLAN2 / 4] = readl(ioaddr + MAC_VLAN2);
6555
}
6656

6757
static int dwmac100_rx_ipc_enable(struct mac_device_info *hw)

‎drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -66,19 +66,18 @@ static void dwmac100_dma_operation_mode(void __iomem *ioaddr, int txmode,
6666
writel(csr6, ioaddr + DMA_CONTROL);
6767
}
6868

69-
static void dwmac100_dump_dma_regs(void __iomem *ioaddr)
69+
static void dwmac100_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
7070
{
7171
int i;
7272

73-
pr_debug("DWMAC 100 DMA CSR\n");
7473
for (i = 0; i < 9; i++)
75-
pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i,
76-
(DMA_BUS_MODE + i * 4),
77-
readl(ioaddr + DMA_BUS_MODE + i * 4));
74+
reg_space[DMA_BUS_MODE / 4 + i] =
75+
readl(ioaddr + DMA_BUS_MODE + i * 4);
7876

79-
pr_debug("\tCSR20 (0x%x): 0x%08x, CSR21 (0x%x): 0x%08x\n",
80-
DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR),
81-
DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR));
77+
reg_space[DMA_CUR_TX_BUF_ADDR / 4] =
78+
readl(ioaddr + DMA_CUR_TX_BUF_ADDR);
79+
reg_space[DMA_CUR_RX_BUF_ADDR / 4] =
80+
readl(ioaddr + DMA_CUR_RX_BUF_ADDR);
8281
}
8382

8483
/* DMA controller has two counters to track the number of the missed frames. */

‎drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -70,19 +70,13 @@ static void dwmac4_rx_queue_enable(struct mac_device_info *hw, u32 queue)
7070
writel(value, ioaddr + GMAC_RXQ_CTRL0);
7171
}
7272

73-
static void dwmac4_dump_regs(struct mac_device_info *hw)
73+
static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
7474
{
7575
void __iomem *ioaddr = hw->pcsr;
7676
int i;
7777

78-
pr_debug("\tDWMAC4 regs (base addr = 0x%p)\n", ioaddr);
79-
80-
for (i = 0; i < GMAC_REG_NUM; i++) {
81-
int offset = i * 4;
82-
83-
pr_debug("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
84-
offset, readl(ioaddr + offset));
85-
}
78+
for (i = 0; i < GMAC_REG_NUM; i++)
79+
reg_space[i] = readl(ioaddr + i * 4);
8680
}
8781

8882
static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)

‎drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c

Lines changed: 38 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -127,53 +127,51 @@ static void dwmac4_dma_init(void __iomem *ioaddr,
127127
dwmac4_dma_init_channel(ioaddr, dma_cfg, dma_tx, dma_rx, i);
128128
}
129129

130-
static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel)
130+
static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel,
131+
u32 *reg_space)
131132
{
132-
pr_debug(" Channel %d\n", channel);
133-
pr_debug("\tDMA_CHAN_CONTROL, offset: 0x%x, val: 0x%x\n", 0,
134-
readl(ioaddr + DMA_CHAN_CONTROL(channel)));
135-
pr_debug("\tDMA_CHAN_TX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x4,
136-
readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)));
137-
pr_debug("\tDMA_CHAN_RX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x8,
138-
readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)));
139-
pr_debug("\tDMA_CHAN_TX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x14,
140-
readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)));
141-
pr_debug("\tDMA_CHAN_RX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x1c,
142-
readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)));
143-
pr_debug("\tDMA_CHAN_TX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x20,
144-
readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)));
145-
pr_debug("\tDMA_CHAN_RX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x28,
146-
readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)));
147-
pr_debug("\tDMA_CHAN_TX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x2c,
148-
readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)));
149-
pr_debug("\tDMA_CHAN_RX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x30,
150-
readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)));
151-
pr_debug("\tDMA_CHAN_INTR_ENA, offset: 0x%x, val: 0x%x\n", 0x34,
152-
readl(ioaddr + DMA_CHAN_INTR_ENA(channel)));
153-
pr_debug("\tDMA_CHAN_RX_WATCHDOG, offset: 0x%x, val: 0x%x\n", 0x38,
154-
readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)));
155-
pr_debug("\tDMA_CHAN_SLOT_CTRL_STATUS, offset: 0x%x, val: 0x%x\n", 0x3c,
156-
readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)));
157-
pr_debug("\tDMA_CHAN_CUR_TX_DESC, offset: 0x%x, val: 0x%x\n", 0x44,
158-
readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)));
159-
pr_debug("\tDMA_CHAN_CUR_RX_DESC, offset: 0x%x, val: 0x%x\n", 0x4c,
160-
readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)));
161-
pr_debug("\tDMA_CHAN_CUR_TX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x54,
162-
readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)));
163-
pr_debug("\tDMA_CHAN_CUR_RX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x5c,
164-
readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)));
165-
pr_debug("\tDMA_CHAN_STATUS, offset: 0x%x, val: 0x%x\n", 0x60,
166-
readl(ioaddr + DMA_CHAN_STATUS(channel)));
133+
reg_space[DMA_CHAN_CONTROL(channel) / 4] =
134+
readl(ioaddr + DMA_CHAN_CONTROL(channel));
135+
reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] =
136+
readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
137+
reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] =
138+
readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));
139+
reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] =
140+
readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));
141+
reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] =
142+
readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
143+
reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] =
144+
readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel));
145+
reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] =
146+
readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel));
147+
reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] =
148+
readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel));
149+
reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] =
150+
readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel));
151+
reg_space[DMA_CHAN_INTR_ENA(channel) / 4] =
152+
readl(ioaddr + DMA_CHAN_INTR_ENA(channel));
153+
reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] =
154+
readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel));
155+
reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] =
156+
readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel));
157+
reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] =
158+
readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel));
159+
reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] =
160+
readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel));
161+
reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] =
162+
readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel));
163+
reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] =
164+
readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel));
165+
reg_space[DMA_CHAN_STATUS(channel) / 4] =
166+
readl(ioaddr + DMA_CHAN_STATUS(channel));
167167
}
168168

169-
static void dwmac4_dump_dma_regs(void __iomem *ioaddr)
169+
static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
170170
{
171171
int i;
172172

173-
pr_debug(" GMAC4 DMA registers\n");
174-
175173
for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
176-
_dwmac4_dump_dma_regs(ioaddr, i);
174+
_dwmac4_dump_dma_regs(ioaddr, i, reg_space);
177175
}
178176

179177
static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt)

‎drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c

Lines changed: 2 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -435,32 +435,14 @@ static int stmmac_ethtool_get_regs_len(struct net_device *dev)
435435
static void stmmac_ethtool_gregs(struct net_device *dev,
436436
struct ethtool_regs *regs, void *space)
437437
{
438-
int i;
439438
u32 *reg_space = (u32 *) space;
440439

441440
struct stmmac_priv *priv = netdev_priv(dev);
442441

443442
memset(reg_space, 0x0, REG_SPACE_SIZE);
444443

445-
if (priv->plat->has_gmac || priv->plat->has_gmac4) {
446-
/* MAC registers */
447-
for (i = 0; i < 55; i++)
448-
reg_space[i] = readl(priv->ioaddr + (i * 4));
449-
/* DMA registers */
450-
for (i = 0; i < 22; i++)
451-
reg_space[i + 55] =
452-
readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4)));
453-
} else {
454-
/* MAC registers */
455-
for (i = 0; i < 12; i++)
456-
reg_space[i] = readl(priv->ioaddr + (i * 4));
457-
/* DMA registers */
458-
for (i = 0; i < 9; i++)
459-
reg_space[i + 12] =
460-
readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4)));
461-
reg_space[22] = readl(priv->ioaddr + DMA_CUR_TX_BUF_ADDR);
462-
reg_space[23] = readl(priv->ioaddr + DMA_CUR_RX_BUF_ADDR);
463-
}
444+
priv->hw->mac->dump_regs(priv->hw, reg_space);
445+
priv->hw->dma->dump_regs(priv->ioaddr, reg_space);
464446
}
465447

466448
static void

‎drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1729,11 +1729,6 @@ static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
17291729
priv->hw->dma->start_tx(priv->ioaddr);
17301730
priv->hw->dma->start_rx(priv->ioaddr);
17311731

1732-
/* Dump DMA/MAC registers */
1733-
if (netif_msg_hw(priv)) {
1734-
priv->hw->mac->dump_regs(priv->hw);
1735-
priv->hw->dma->dump_regs(priv->ioaddr);
1736-
}
17371732
priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
17381733

17391734
if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {

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