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net: phy: mediatek-ge-soc: sync driver with MediaTek SDK
Sync initialization and calibration routines with MediaTek's reference driver. Improves compliance and resolves link stability issues with CH340 IoT devices connected to MT798x built-in PHYs. Fixes: 98c485e ("net: phy: add driver for MediaTek SoC built-in GE PHYs") Signed-off-by: Daniel Golle <[email protected]> Link: https://lore.kernel.org/r/f2195279c234c0f618946424b8236026126bc595.1706071311.git.daniel@makrotopia.org Signed-off-by: Jakub Kicinski <[email protected]>
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‎drivers/net/phy/mediatek-ge-soc.c

Lines changed: 81 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -489,7 +489,7 @@ static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
489489
u16 reg, val;
490490

491491
if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
492-
bias = -2;
492+
bias = -1;
493493

494494
val = clamp_val(bias + tx_r50_cal_val, 0, 63);
495495

@@ -705,6 +705,11 @@ static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
705705
static void mt798x_phy_common_finetune(struct phy_device *phydev)
706706
{
707707
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
708+
/* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
709+
__phy_write(phydev, 0x11, 0xc71);
710+
__phy_write(phydev, 0x12, 0xc);
711+
__phy_write(phydev, 0x10, 0x8fae);
712+
708713
/* EnabRandUpdTrig = 1 */
709714
__phy_write(phydev, 0x11, 0x2f00);
710715
__phy_write(phydev, 0x12, 0xe);
@@ -715,15 +720,56 @@ static void mt798x_phy_common_finetune(struct phy_device *phydev)
715720
__phy_write(phydev, 0x12, 0x0);
716721
__phy_write(phydev, 0x10, 0x83aa);
717722

718-
/* TrFreeze = 0 */
723+
/* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
724+
__phy_write(phydev, 0x11, 0x240);
725+
__phy_write(phydev, 0x12, 0x0);
726+
__phy_write(phydev, 0x10, 0x9680);
727+
728+
/* TrFreeze = 0 (mt7988 default) */
719729
__phy_write(phydev, 0x11, 0x0);
720730
__phy_write(phydev, 0x12, 0x0);
721731
__phy_write(phydev, 0x10, 0x9686);
722732

733+
/* SSTrKp100 = 5 */
734+
/* SSTrKf100 = 6 */
735+
/* SSTrKp1000Mas = 5 */
736+
/* SSTrKf1000Mas = 6 */
723737
/* SSTrKp1000Slv = 5 */
738+
/* SSTrKf1000Slv = 6 */
724739
__phy_write(phydev, 0x11, 0xbaef);
725740
__phy_write(phydev, 0x12, 0x2e);
726741
__phy_write(phydev, 0x10, 0x968c);
742+
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
743+
}
744+
745+
static void mt7981_phy_finetune(struct phy_device *phydev)
746+
{
747+
u16 val[8] = { 0x01ce, 0x01c1,
748+
0x020f, 0x0202,
749+
0x03d0, 0x03c0,
750+
0x0013, 0x0005 };
751+
int i, k;
752+
753+
/* 100M eye finetune:
754+
* Keep middle level of TX MLT3 shapper as default.
755+
* Only change TX MLT3 overshoot level here.
756+
*/
757+
for (k = 0, i = 1; i < 12; i++) {
758+
if (i % 3 == 0)
759+
continue;
760+
phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
761+
}
762+
763+
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
764+
/* ResetSyncOffset = 6 */
765+
__phy_write(phydev, 0x11, 0x600);
766+
__phy_write(phydev, 0x12, 0x0);
767+
__phy_write(phydev, 0x10, 0x8fc0);
768+
769+
/* VgaDecRate = 1 */
770+
__phy_write(phydev, 0x11, 0x4c2a);
771+
__phy_write(phydev, 0x12, 0x3e);
772+
__phy_write(phydev, 0x10, 0x8fa4);
727773

728774
/* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
729775
* MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
@@ -738,7 +784,7 @@ static void mt798x_phy_common_finetune(struct phy_device *phydev)
738784
__phy_write(phydev, 0x10, 0x8ec0);
739785
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
740786

741-
/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
787+
/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
742788
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
743789
MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
744790
BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
@@ -771,48 +817,6 @@ static void mt798x_phy_common_finetune(struct phy_device *phydev)
771817
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
772818
}
773819

774-
static void mt7981_phy_finetune(struct phy_device *phydev)
775-
{
776-
u16 val[8] = { 0x01ce, 0x01c1,
777-
0x020f, 0x0202,
778-
0x03d0, 0x03c0,
779-
0x0013, 0x0005 };
780-
int i, k;
781-
782-
/* 100M eye finetune:
783-
* Keep middle level of TX MLT3 shapper as default.
784-
* Only change TX MLT3 overshoot level here.
785-
*/
786-
for (k = 0, i = 1; i < 12; i++) {
787-
if (i % 3 == 0)
788-
continue;
789-
phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
790-
}
791-
792-
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
793-
/* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
794-
__phy_write(phydev, 0x11, 0xc71);
795-
__phy_write(phydev, 0x12, 0xc);
796-
__phy_write(phydev, 0x10, 0x8fae);
797-
798-
/* ResetSyncOffset = 6 */
799-
__phy_write(phydev, 0x11, 0x600);
800-
__phy_write(phydev, 0x12, 0x0);
801-
__phy_write(phydev, 0x10, 0x8fc0);
802-
803-
/* VgaDecRate = 1 */
804-
__phy_write(phydev, 0x11, 0x4c2a);
805-
__phy_write(phydev, 0x12, 0x3e);
806-
__phy_write(phydev, 0x10, 0x8fa4);
807-
808-
/* FfeUpdGainForce = 4 */
809-
__phy_write(phydev, 0x11, 0x240);
810-
__phy_write(phydev, 0x12, 0x0);
811-
__phy_write(phydev, 0x10, 0x9680);
812-
813-
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
814-
}
815-
816820
static void mt7988_phy_finetune(struct phy_device *phydev)
817821
{
818822
u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
@@ -827,31 +831,35 @@ static void mt7988_phy_finetune(struct phy_device *phydev)
827831
/* TCT finetune */
828832
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
829833

830-
/* Disable TX power saving */
831-
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
832-
MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
833-
834834
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
835-
836-
/* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
837-
__phy_write(phydev, 0x11, 0x671);
838-
__phy_write(phydev, 0x12, 0xc);
839-
__phy_write(phydev, 0x10, 0x8fae);
840-
841835
/* ResetSyncOffset = 5 */
842836
__phy_write(phydev, 0x11, 0x500);
843837
__phy_write(phydev, 0x12, 0x0);
844838
__phy_write(phydev, 0x10, 0x8fc0);
845839

846840
/* VgaDecRate is 1 at default on mt7988 */
847841

848-
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
842+
/* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
843+
* MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
844+
*/
845+
__phy_write(phydev, 0x11, 0xb90a);
846+
__phy_write(phydev, 0x12, 0x6f);
847+
__phy_write(phydev, 0x10, 0x8f82);
848+
849+
/* RemAckCntLimitCtrl = 1 */
850+
__phy_write(phydev, 0x11, 0xfbba);
851+
__phy_write(phydev, 0x12, 0xc3);
852+
__phy_write(phydev, 0x10, 0x87f8);
849853

850-
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
851-
/* TxClkOffset = 2 */
852-
__phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
853-
FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
854854
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
855+
856+
/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
857+
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
858+
MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
859+
BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
860+
861+
/* rg_tr_lpf_cnt_val = 1023 */
862+
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
855863
}
856864

857865
static void mt798x_phy_eee(struct phy_device *phydev)
@@ -884,11 +892,11 @@ static void mt798x_phy_eee(struct phy_device *phydev)
884892
MTK_PHY_LPI_SLV_SEND_TX_EN,
885893
FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
886894

887-
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
888-
MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
889-
MTK_PHY_LPI_TXPCS_LOC_RCV,
890-
FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
895+
/* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
896+
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
897+
MTK_PHY_LPI_TXPCS_LOC_RCV);
891898

899+
/* This also fixes some IoT issues, such as CH340 */
892900
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
893901
MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
894902
FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
@@ -922,7 +930,7 @@ static void mt798x_phy_eee(struct phy_device *phydev)
922930
__phy_write(phydev, 0x12, 0x0);
923931
__phy_write(phydev, 0x10, 0x9690);
924932

925-
/* REG_EEE_st2TrKf1000 = 3 */
933+
/* REG_EEE_st2TrKf1000 = 2 */
926934
__phy_write(phydev, 0x11, 0x114f);
927935
__phy_write(phydev, 0x12, 0x2);
928936
__phy_write(phydev, 0x10, 0x969a);
@@ -947,7 +955,7 @@ static void mt798x_phy_eee(struct phy_device *phydev)
947955
__phy_write(phydev, 0x12, 0x0);
948956
__phy_write(phydev, 0x10, 0x96b8);
949957

950-
/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
958+
/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
951959
__phy_write(phydev, 0x11, 0x1463);
952960
__phy_write(phydev, 0x12, 0x0);
953961
__phy_write(phydev, 0x10, 0x96ca);
@@ -1459,6 +1467,13 @@ static int mt7988_phy_probe(struct phy_device *phydev)
14591467
if (err)
14601468
return err;
14611469

1470+
/* Disable TX power saving at probing to:
1471+
* 1. Meet common mode compliance test criteria
1472+
* 2. Make sure that TX-VCM calibration works fine
1473+
*/
1474+
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
1475+
MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
1476+
14621477
return mt798x_phy_calibration(phydev);
14631478
}
14641479

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