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refactor: StdLogicVector and StdULogicVector
- adds setindex! and related tests - logic and levels are now `Array` - predefined logic vectors are now consts
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+41
-24
lines changed

3 files changed

+41
-24
lines changed
Lines changed: 24 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,23 +1,23 @@
1-
import Base: size, axes, getindex
1+
import Base: size, axes, getindex, setindex!
22

33
const LogicOrNumber = Union{Logic, Number}
44

55
struct StdULogicVector{N} <: AbstractArray{Logic, N}
6-
logic::AbstractArray{Logic}
7-
level::AbstractArray{Int}
8-
function StdULogicVector(l::AbstractArray)
6+
logic::Array{Logic}
7+
level::Array{Int}
8+
function StdULogicVector(l::Array)
99
N = ndims(l)
10-
l = AbstractArray{Logic}(convert.(Logic, l))
10+
l = Array{Logic}(convert.(Logic, l))
1111
new{N}(l, get_logic_level.(l))
1212
end
1313
end
1414

1515
struct StdLogicVector{N} <: AbstractArray{Logic, N}
16-
logic::AbstractArray{Logic}
17-
level::AbstractArray{Int}
18-
function StdLogicVector(l::AbstractArray)
16+
logic::Array{Logic}
17+
level::Array{Int}
18+
function StdLogicVector(l::Array)
1919
N = ndims(l)
20-
l = AbstractArray{Logic}(convert.(Logic, l))
20+
l = Array{Logic}(convert.(Logic, l))
2121
new{N}(l, get_logic_level.(l))
2222
end
2323
end
@@ -37,11 +37,21 @@ function Base.getindex(s::LogicVector, i1::Int, i2::Int,
3737
getindex(s.logic, i1, i2, I...)
3838
end
3939

40+
function Base.setindex!(A::LogicVector, x::Logic, i1::Int)
41+
setindex!(A.logic, x, i1)
42+
setindex!(A.level, get_logic_level(x), i1)
43+
end
44+
45+
function Base.setindex!(A::LogicVector, x::Logic, i1::Int, i2::Int, I::Int...)
46+
setindex!(A.logic, x, i1, i2, I...)
47+
setindex!(A.level, get_logic_level(x), i1, i2, I...)
48+
end
49+
4050
get_logic_level(s::LogicVector) = s.level
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4252
# predefined vectors
43-
std_ulogic = StdULogicVector([U, X, F0, F1, Z, W, L, H, DC])
44-
UX01 = StdULogicVector([U, X, F0, F1])
45-
UX01Z = StdULogicVector([U, X, F0, F1, Z])
46-
X01 = StdULogicVector([X, F0, F1])
47-
X01Z = StdULogicVector([X, F0, F1, Z])
53+
const std_ulogic = StdULogicVector([U, X, F0, F1, Z, W, L, H, DC])
54+
const UX01 = StdULogicVector([U, X, F0, F1])
55+
const UX01Z = StdULogicVector([U, X, F0, F1, Z])
56+
const X01 = StdULogicVector([X, F0, F1])
57+
const X01Z = StdULogicVector([X, F0, F1, Z])

src/Electrical/Electrical.jl

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,6 @@ include("Analog/sensors.jl")
2525
export Voltage, Current
2626
include("Analog/sources.jl")
2727

28-
# include("Digital/logic_vectors.jl")
2928
# include("Digital/gates.jl")
3029
# include("Digital/sources.jl")
3130

@@ -38,7 +37,8 @@ export Logic
3837
include("Digital/logic.jl")
3938

4039
export StdLogicVector, StdULogicVector,
41-
std_ulogic, UX01, UX01Z, X01, X01Z
40+
std_ulogic, UX01, UX01Z, X01, X01Z,
41+
get_logic_level
4242
include("Digital/logic_vectors.jl")
4343

4444
include("Digital/tables.jl")

test/Electrical/digital.jl

Lines changed: 15 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -38,13 +38,20 @@ using ModelingToolkitStandardLibrary.Electrical: get_logic_level
3838
@test X01Z.logic == [X, F0, F1, Z]
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4040
# Logic vector helpers
41-
logic_vector = StdULogicVector([U F0
42-
F1 X])
43-
size(logic_vector) == (2, 2)
44-
axes(logic_vector) == (Base.OneTo(2), Base.OneTo(2))
45-
getindex(logic_vector, 1, 1) == U
41+
test_logic_matrix = StdULogicVector([U F0
42+
F1 X])
43+
test_logic_vector = StdLogicVector([U, F0, F1, X])
4644

47-
getindex(StdLogicVector([U, F0, F1, X]), 1) == U
45+
size(test_logic_matrix) == (2, 2)
46+
axes(test_logic_matrix) == (Base.OneTo(2), Base.OneTo(2))
47+
48+
getindex(test_logic_matrix, 1, 1) == U
49+
getindex(test_logic_vector, 1) == U
50+
51+
setindex!(test_logic_matrix, Z, 1, 1)
52+
@test test_logic_matrix[1, 1] == Z
53+
setindex!(test_logic_vector, Z, 1)
54+
@test test_logic_vector[1] == Z
4855

4956
# Logic helper functions
5057
@test get_logic_level.([U, X, F0, F1, Z, W, L, H, DC]) == 1:9
@@ -62,8 +69,8 @@ end
6269
@test _or(0, 1, U, 1) == F1
6370
@test _xor(0, 1, U, U, 1, 1) == U
6471
# tests (Number, Logic) input
65-
@info _and(1, F1) == F1
66-
@info _or(0, F0) == F0
72+
@test _and(1, F1) == F1
73+
@test _or(0, F0) == F0
6774
@test _xor(1, F0) == F1
6875
# tests Number and Logic (via internal convert)
6976
@test _not(1) == F0

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