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test: increase the test coverage
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test/Electrical/digital.jl

Lines changed: 15 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2,13 +2,13 @@ using ModelingToolkitStandardLibrary.Electrical, ModelingToolkit, OrdinaryDiffEq
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using ModelingToolkitStandardLibrary.Electrical: _and, _or, _not, _xor
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using ModelingToolkitStandardLibrary.Electrical: U, X, F0, F1, Z, W, L, H, DC
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using ModelingToolkitStandardLibrary.Electrical: AndTable, OrTable, NotTable, XorTable
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using ModelingToolkitStandardLibrary.Electrical: convert_to_logic, get_logic_level
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using ModelingToolkitStandardLibrary.Electrical: get_logic_level
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# using ModelingToolkitStandardLibrary.Electrical: Set, Reset
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@testset "Logic, logic-vectors and helpers" begin
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# Logic and helper functions
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@test length(instances(Logic)) == 9
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@test convert_to_logic.([1, 0]) |> typeof == Vector{Logic}
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@test convert.(Logic, [1, 0]) |> typeof == Vector{Logic}
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@test get_logic_level(Z) == 5
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# Logic zeros and ones
@@ -33,18 +33,27 @@ using ModelingToolkitStandardLibrary.Electrical: convert_to_logic, get_logic_lev
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@test X01.logic == [X, F0, F1]
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@test X01Z.logic == [X, F0, F1, Z]
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# Logic vector helpers
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logic_vector = [U F0
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F1 X]
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size(logic_vector) == (2, 2)
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axes(logic_vector) == (Base.OneTo(2), Base.OneTo(2))
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getindex(logic_vector, 1, 1) == U
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# Logic helper functions
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@test get_logic_level.([U, X, F0, F1, Z, W, L, H, DC]) == 1:9
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@test convert_to_logic.([1, 0, U]) == [F1, F0, U]
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@test convert.(Logic, [1, 0, U]) == [F1, F0, U]
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@test_throws "3 isn't a valid `Logic` value" convert(Logic, 3)
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end
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@testset "Logic tables and logic gate helpers" begin
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# logic tables and logic gate helpers
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@test size(AndTable) == size(OrTable) == size(XorTable) == (9, 9)
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@test size(NotTable) == (9,)
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@test _and(1, 1, 1, 1, 1, 0) == F0
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@test _or(0, 1, 1, 1) == F1
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@test _xor(0, 1, 1, 1, 1, 1) == F1
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@test _and(1, 1, U, W, 1, 0) == F0
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@test _or(0, U, 1, 1) == F1
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@test _xor(0, 1, U, U, 1, 1) == U
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@test _not(1) == F0
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A = [U, W, Z, F1, F0]

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