Skip to content

Commit 018230a

Browse files
committed
Revert "Merge pull request #407 from Xilinx/matthias.fix_non_monotonic_slice_params"
This reverts commit 573742a, reversing changes made to 1bf1742.
1 parent a067405 commit 018230a

File tree

6 files changed

+1
-82
lines changed

6 files changed

+1
-82
lines changed

mlir/include/mlir/IR/AffineExpr.h

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -110,11 +110,6 @@ class AffineExpr {
110110
/// floordiv, ceildiv, and mod is only allowed w.r.t constants.
111111
bool isPureAffine() const;
112112

113-
/// Returns true if this expression is monotonicically increasing with respect
114-
/// to the AffineDimExprs, i.e. increasing the value of any AffineDimExpr will
115-
/// never decrease the value of the result.
116-
bool isMonotonicallyIncreasing() const;
117-
118113
/// Returns the greatest known integral divisor of this affine expression. The
119114
/// result is always positive.
120115
int64_t getLargestKnownDivisor() const;

mlir/include/mlir/IR/AffineMap.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -382,10 +382,6 @@ class AffineMap {
382382
/// Returns true if the AffineMap represents a symbol-less permutation map.
383383
bool isPermutation() const;
384384

385-
// Returns true if every result is monotonically increasing.
386-
// See AffineExpr::isMonotonicallyIncreasing().
387-
bool isComponentWiseMonotonicallyIncreasing() const;
388-
389385
/// Returns the map consisting of the `resultPos` subset.
390386
AffineMap getSubMap(ArrayRef<unsigned> resultPos) const;
391387

mlir/lib/Dialect/Linalg/Utils/Utils.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -612,6 +612,7 @@ SliceParameters computeSliceParameters(
612612

613613
// Tiling creates a new slice at the proper index, the slice step is 1
614614
// (i.e. the op does not subsample, stepping occurs in the loop).
615+
auto m = map.getSubMap({r});
615616
LLVM_DEBUG(llvm::dbgs() << "computeSliceParameters: submap: " << m << "\n");
616617
IRRewriter rewriter(builder);
617618
// The offset of the slice is map(lbs) - map(0).

mlir/lib/IR/AffineExpr.cpp

Lines changed: 0 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -239,42 +239,6 @@ bool AffineExpr::isPureAffine() const {
239239
llvm_unreachable("Unknown AffineExpr");
240240
}
241241

242-
static bool isNonNegativeConstant(AffineExpr expr) {
243-
auto constant = dyn_cast<AffineConstantExpr>(expr);
244-
return constant && constant.getValue() >= 0;
245-
}
246-
247-
bool AffineExpr::isMonotonicallyIncreasing() const {
248-
switch (getKind()) {
249-
case AffineExprKind::SymbolId:
250-
case AffineExprKind::DimId:
251-
case AffineExprKind::Constant:
252-
return true;
253-
case AffineExprKind::Add: {
254-
auto op = llvm::cast<AffineBinaryOpExpr>(*this);
255-
return op.getLHS().isMonotonicallyIncreasing() &&
256-
op.getRHS().isMonotonicallyIncreasing();
257-
}
258-
case AffineExprKind::Mul: {
259-
// One operand must be a non-negative constant.
260-
auto op = llvm::cast<AffineBinaryOpExpr>(*this);
261-
return op.getLHS().isMonotonicallyIncreasing() &&
262-
op.getRHS().isMonotonicallyIncreasing() &&
263-
(isNonNegativeConstant(op.getLHS()) ||
264-
isNonNegativeConstant(op.getRHS()));
265-
}
266-
case AffineExprKind::FloorDiv:
267-
case AffineExprKind::CeilDiv: {
268-
auto op = llvm::cast<AffineBinaryOpExpr>(*this);
269-
return op.getLHS().isMonotonicallyIncreasing() &&
270-
isNonNegativeConstant(op.getRHS());
271-
}
272-
case AffineExprKind::Mod:
273-
return false;
274-
}
275-
llvm_unreachable("Unknown AffineExpr");
276-
}
277-
278242
// Returns the greatest known integral divisor of this affine expression.
279243
int64_t AffineExpr::getLargestKnownDivisor() const {
280244
AffineBinaryOpExpr binExpr(nullptr);

mlir/lib/IR/AffineMap.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -651,11 +651,6 @@ bool AffineMap::isPermutation() const {
651651
return isProjectedPermutation();
652652
}
653653

654-
bool AffineMap::isComponentWiseMonotonicallyIncreasing() const {
655-
return all_of(getResults(),
656-
[](auto expr) { return expr.isMonotonicallyIncreasing(); });
657-
}
658-
659654
AffineMap AffineMap::getSubMap(ArrayRef<unsigned> resultPos) const {
660655
SmallVector<AffineExpr, 4> exprs;
661656
exprs.reserve(resultPos.size());

mlir/test/Dialect/Linalg/tile-tensors.mlir

Lines changed: 0 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -167,35 +167,3 @@ module attributes {transform.with_named_sequence} {
167167
transform.yield
168168
}
169169
}
170-
171-
// -----
172-
173-
// CHECK-LABEL: func @non_monotonic_affine_expr
174-
// CHECK-SAME: %[[ARG0:[a-zA-Z0-9_]+]]: tensor<?xf32>
175-
func.func @non_monotonic_affine_expr(%arg0 : tensor<?xf32>) -> tensor<?xf32> {
176-
%c0 = arith.constant 0 : index
177-
%0 = tensor.dim %arg0, %c0 : tensor<?xf32>
178-
%empty = tensor.empty(%0) : tensor<?xf32>
179-
180-
// CHECK: scf.for
181-
// CHECK: %[[SIZE:[a-zA-Z0-9_]+]] = tensor.dim %[[ARG0]],
182-
// CHECK: tensor.extract_slice %[[ARG0]][0] [%[[SIZE]]] [1] : tensor<?xf32> to tensor<?xf32>
183-
%generic = linalg.generic
184-
{indexing_maps = [affine_map<(d0) -> (d0 mod 3)>,
185-
affine_map<(d0) -> (d0)>],
186-
iterator_types = ["parallel"]}
187-
ins(%arg0: tensor<?xf32>)
188-
outs(%empty : tensor<?xf32>) {
189-
^bb0(%in : f32, %out: f32):
190-
linalg.yield %in : f32
191-
} -> tensor<?xf32>
192-
return %generic : tensor<?xf32>
193-
}
194-
195-
module attributes {transform.with_named_sequence} {
196-
transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) {
197-
%0 = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op
198-
%1, %loop = transform.structured.tile_using_for %0 tile_sizes [100] : (!transform.any_op) -> (!transform.any_op, !transform.any_op)
199-
transform.yield
200-
}
201-
}

0 commit comments

Comments
 (0)