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[X86][MC] Simplify some code in X86AsmBackend.cpp, NFCI
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llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

Lines changed: 26 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -209,47 +209,42 @@ class X86AsmBackend : public MCAsmBackend {
209209
};
210210
} // end anonymous namespace
211211

212-
static unsigned getRelaxedOpcodeBranch(const MCInst &Inst, bool Is16BitMode) {
213-
unsigned Op = Inst.getOpcode();
214-
switch (Op) {
212+
static bool isRelaxableBranch(unsigned Opcode) {
213+
return Opcode == X86::JCC_1 || Opcode == X86::JMP_1;
214+
}
215+
216+
static unsigned getRelaxedOpcodeBranch(unsigned Opcode,
217+
bool Is16BitMode = false) {
218+
switch (Opcode) {
215219
default:
216-
return Op;
220+
llvm_unreachable("invalid opcode for branch");
217221
case X86::JCC_1:
218222
return (Is16BitMode) ? X86::JCC_2 : X86::JCC_4;
219223
case X86::JMP_1:
220224
return (Is16BitMode) ? X86::JMP_2 : X86::JMP_4;
221225
}
222226
}
223227

224-
static unsigned getOpcodeForLongImmediateForm(const MCInst &Inst) {
225-
unsigned Op = Inst.getOpcode();
226-
return X86::getOpcodeForLongImmediateForm(Op);
227-
}
228-
229-
static unsigned getRelaxedOpcode(const MCInst &Inst, bool Is16BitMode) {
230-
unsigned R = getOpcodeForLongImmediateForm(Inst);
231-
if (R != Inst.getOpcode())
232-
return R;
233-
return getRelaxedOpcodeBranch(Inst, Is16BitMode);
228+
static unsigned getRelaxedOpcode(const MCInst &MI, bool Is16BitMode) {
229+
unsigned Opcode = MI.getOpcode();
230+
return isRelaxableBranch(Opcode) ? getRelaxedOpcodeBranch(Opcode, Is16BitMode)
231+
: X86::getOpcodeForLongImmediateForm(Opcode);
234232
}
235233

236-
static X86::CondCode getCondFromBranch(const MCInst &MI,
237-
const MCInstrInfo &MCII) {
234+
static X86::CondCode getCondFromBranch(const MCInst &MI) {
238235
unsigned Opcode = MI.getOpcode();
239236
switch (Opcode) {
240237
default:
241238
return X86::COND_INVALID;
242-
case X86::JCC_1: {
243-
const MCInstrDesc &Desc = MCII.get(Opcode);
239+
case X86::JCC_1:
244240
return static_cast<X86::CondCode>(
245-
MI.getOperand(Desc.getNumOperands() - 1).getImm());
246-
}
241+
MI.getOperand(MI.getNumOperands() - 1).getImm());
247242
}
248243
}
249244

250245
static X86::SecondMacroFusionInstKind
251-
classifySecondInstInMacroFusion(const MCInst &MI, const MCInstrInfo &MCII) {
252-
X86::CondCode CC = getCondFromBranch(MI, MCII);
246+
classifySecondInstInMacroFusion(const MCInst &MI) {
247+
X86::CondCode CC = getCondFromBranch(MI);
253248
return classifySecondCondCodeInMacroFusion(CC);
254249
}
255250

@@ -356,7 +351,7 @@ bool X86AsmBackend::isMacroFused(const MCInst &Cmp, const MCInst &Jcc) const {
356351
const X86::FirstMacroFusionInstKind CmpKind =
357352
X86::classifyFirstOpcodeInMacroFusion(Cmp.getOpcode());
358353
const X86::SecondMacroFusionInstKind BranchKind =
359-
classifySecondInstInMacroFusion(Jcc, *MCII);
354+
classifySecondInstInMacroFusion(Jcc);
360355
return X86::isMacroFused(CmpKind, BranchKind);
361356
}
362357

@@ -721,24 +716,12 @@ void X86AsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
721716
Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
722717
}
723718

724-
bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst,
719+
bool X86AsmBackend::mayNeedRelaxation(const MCInst &MI,
725720
const MCSubtargetInfo &STI) const {
726-
// Branches can always be relaxed in either mode.
727-
if (getRelaxedOpcodeBranch(Inst, false) != Inst.getOpcode())
728-
return true;
729-
730-
// Check if this instruction is ever relaxable.
731-
if (getOpcodeForLongImmediateForm(Inst) == Inst.getOpcode())
732-
return false;
733-
734-
735-
// Check if the relaxable operand has an expression. For the current set of
736-
// relaxable instructions, the relaxable operand is always the last operand.
737-
unsigned RelaxableOp = Inst.getNumOperands() - 1;
738-
if (Inst.getOperand(RelaxableOp).isExpr())
739-
return true;
740-
741-
return false;
721+
unsigned Opcode = MI.getOpcode();
722+
return isRelaxableBranch(Opcode) ||
723+
(X86::getOpcodeForLongImmediateForm(Opcode) != Opcode &&
724+
MI.getOperand(MI.getNumOperands() - 1).isExpr());
742725
}
743726

744727
bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
@@ -768,15 +751,6 @@ void X86AsmBackend::relaxInstruction(MCInst &Inst,
768751
Inst.setOpcode(RelaxedOp);
769752
}
770753

771-
/// Return true if this instruction has been fully relaxed into it's most
772-
/// general available form.
773-
static bool isFullyRelaxed(const MCRelaxableFragment &RF) {
774-
auto &Inst = RF.getInst();
775-
auto &STI = *RF.getSubtargetInfo();
776-
bool Is16BitMode = STI.hasFeature(X86::Is16Bit);
777-
return getRelaxedOpcode(Inst, Is16BitMode) == Inst.getOpcode();
778-
}
779-
780754
bool X86AsmBackend::padInstructionViaPrefix(MCRelaxableFragment &RF,
781755
MCCodeEmitter &Emitter,
782756
unsigned &RemainingSize) const {
@@ -786,7 +760,7 @@ bool X86AsmBackend::padInstructionViaPrefix(MCRelaxableFragment &RF,
786760
// larger value for one of the fixups then can be encoded. The outer loop
787761
// will also catch this before moving to the next instruction, but we need to
788762
// prevent padding this single instruction as well.
789-
if (!isFullyRelaxed(RF))
763+
if (mayNeedRelaxation(RF.getInst(), *RF.getSubtargetInfo()))
790764
return false;
791765

792766
const unsigned OldSize = RF.getContents().size();
@@ -833,7 +807,7 @@ bool X86AsmBackend::padInstructionViaPrefix(MCRelaxableFragment &RF,
833807
bool X86AsmBackend::padInstructionViaRelaxation(MCRelaxableFragment &RF,
834808
MCCodeEmitter &Emitter,
835809
unsigned &RemainingSize) const {
836-
if (isFullyRelaxed(RF))
810+
if (!mayNeedRelaxation(RF.getInst(), *RF.getSubtargetInfo()))
837811
// TODO: There are lots of other tricks we could apply for increasing
838812
// encoding size without impacting performance.
839813
return false;
@@ -949,7 +923,7 @@ void X86AsmBackend::finishLayout(MCAssembler const &Asm,
949923
// We don't need to worry about larger positive offsets as none of the
950924
// possible offsets between this and our align are visible, and the
951925
// ones afterwards aren't changing.
952-
if (!isFullyRelaxed(RF))
926+
if (mayNeedRelaxation(RF.getInst(), *RF.getSubtargetInfo()))
953927
break;
954928
}
955929
Relaxable.clear();

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