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Pierre-vhPierre-vh
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[NFC] clang-format GlobalISelEmitter.cpp
It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
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‎llvm/utils/TableGen/GlobalISelEmitter.cpp

Lines changed: 84 additions & 76 deletions
Original file line numberDiff line numberDiff line change
@@ -290,8 +290,7 @@ static Expected<LLTCodeGen> getInstResultType(const TreePatternNode *Dst) {
290290

291291
std::optional<LLTCodeGen> MaybeOpTy;
292292
if (ChildTypes.front().isMachineValueType()) {
293-
MaybeOpTy =
294-
MVTToLLT(ChildTypes.front().getMachineValueType().SimpleTy);
293+
MaybeOpTy = MVTToLLT(ChildTypes.front().getMachineValueType().SimpleTy);
295294
}
296295

297296
if (!MaybeOpTy)
@@ -468,15 +467,15 @@ void GlobalISelEmitter::gatherNodeEquivs() {
468467
if (!SelDAGEquiv)
469468
continue;
470469
ComplexPatternEquivs[SelDAGEquiv] = Equiv;
471-
}
472-
473-
assert(SDNodeXFormEquivs.empty());
474-
for (Record *Equiv : RK.getAllDerivedDefinitions("GISDNodeXFormEquiv")) {
475-
Record *SelDAGEquiv = Equiv->getValueAsDef("SelDAGEquivalent");
476-
if (!SelDAGEquiv)
477-
continue;
478-
SDNodeXFormEquivs[SelDAGEquiv] = Equiv;
479-
}
470+
}
471+
472+
assert(SDNodeXFormEquivs.empty());
473+
for (Record *Equiv : RK.getAllDerivedDefinitions("GISDNodeXFormEquiv")) {
474+
Record *SelDAGEquiv = Equiv->getValueAsDef("SelDAGEquivalent");
475+
if (!SelDAGEquiv)
476+
continue;
477+
SDNodeXFormEquivs[SelDAGEquiv] = Equiv;
478+
}
480479
}
481480

482481
Record *GlobalISelEmitter::findNodeEquiv(Record *N) const {
@@ -772,12 +771,14 @@ Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
772771
}
773772

774773
bool IsAtomic = false;
775-
if (SrcGIEquivOrNull && SrcGIEquivOrNull->getValueAsBit("CheckMMOIsNonAtomic"))
774+
if (SrcGIEquivOrNull &&
775+
SrcGIEquivOrNull->getValueAsBit("CheckMMOIsNonAtomic"))
776776
InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>("NotAtomic");
777-
else if (SrcGIEquivOrNull && SrcGIEquivOrNull->getValueAsBit("CheckMMOIsAtomic")) {
777+
else if (SrcGIEquivOrNull &&
778+
SrcGIEquivOrNull->getValueAsBit("CheckMMOIsAtomic")) {
778779
IsAtomic = true;
779780
InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>(
780-
"Unordered", AtomicOrderingMMOPredicateMatcher::AO_OrStronger);
781+
"Unordered", AtomicOrderingMMOPredicateMatcher::AO_OrStronger);
781782
}
782783

783784
if (Src->isLeaf()) {
@@ -817,9 +818,9 @@ Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
817818
return failedImport("Unable to handle CondCode");
818819

819820
OperandMatcher &OM =
820-
InsnMatcher.addOperand(OpIdx++, SrcChild->getName(), TempOpIdx);
821-
StringRef PredType = IsFCmp ? CCDef->getValueAsString("FCmpPredicate") :
822-
CCDef->getValueAsString("ICmpPredicate");
821+
InsnMatcher.addOperand(OpIdx++, SrcChild->getName(), TempOpIdx);
822+
StringRef PredType = IsFCmp ? CCDef->getValueAsString("FCmpPredicate")
823+
: CCDef->getValueAsString("ICmpPredicate");
823824

824825
if (!PredType.empty()) {
825826
OM.addPredicate<CmpPredicateOperandMatcher>(std::string(PredType));
@@ -871,8 +872,9 @@ Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
871872
bool OperandIsImmArg = SrcGIOrNull->isInOperandImmArg(i);
872873

873874
// SelectionDAG allows pointers to be represented with iN since it doesn't
874-
// distinguish between pointers and integers but they are different types in GlobalISel.
875-
// Coerce integers to pointers to address space 0 if the context indicates a pointer.
875+
// distinguish between pointers and integers but they are different types
876+
// in GlobalISel. Coerce integers to pointers to address space 0 if the
877+
// context indicates a pointer.
876878
//
877879
bool OperandIsAPointer = SrcGIOrNull->isInOperandAPointer(i);
878880

@@ -1029,7 +1031,8 @@ Error GlobalISelEmitter::importChildMatcher(
10291031
// This isn't strictly true. If the user were to provide exactly the same
10301032
// matchers as the original operand then we could allow it. However, it's
10311033
// simpler to not permit the redundant specification.
1032-
return failedImport("Nested instruction cannot be the same as another operand");
1034+
return failedImport(
1035+
"Nested instruction cannot be the same as another operand");
10331036
}
10341037

10351038
// Map the node to a gMIR instruction.
@@ -1079,11 +1082,11 @@ Error GlobalISelEmitter::importChildMatcher(
10791082
if (ChildRec->isSubClassOf("Register")) {
10801083
// This just be emitted as a copy to the specific register.
10811084
ValueTypeByHwMode VT = ChildTypes.front().getValueTypeByHwMode();
1082-
const CodeGenRegisterClass *RC
1083-
= CGRegs.getMinimalPhysRegClass(ChildRec, &VT);
1085+
const CodeGenRegisterClass *RC =
1086+
CGRegs.getMinimalPhysRegClass(ChildRec, &VT);
10841087
if (!RC) {
10851088
return failedImport(
1086-
"Could not determine physical register class of pattern source");
1089+
"Could not determine physical register class of pattern source");
10871090
}
10881091

10891092
OM.addPredicate<RegisterBankOperandMatcher>(*RC);
@@ -1118,10 +1121,10 @@ Error GlobalISelEmitter::importChildMatcher(
11181121

11191122
ValueTypeByHwMode VTy = ChildTypes.front().getValueTypeByHwMode();
11201123

1121-
const CodeGenInstruction &BuildVector
1122-
= Target.getInstruction(RK.getDef("G_BUILD_VECTOR"));
1123-
const CodeGenInstruction &BuildVectorTrunc
1124-
= Target.getInstruction(RK.getDef("G_BUILD_VECTOR_TRUNC"));
1124+
const CodeGenInstruction &BuildVector =
1125+
Target.getInstruction(RK.getDef("G_BUILD_VECTOR"));
1126+
const CodeGenInstruction &BuildVectorTrunc =
1127+
Target.getInstruction(RK.getDef("G_BUILD_VECTOR_TRUNC"));
11251128

11261129
// Treat G_BUILD_VECTOR as the canonical opcode, and G_BUILD_VECTOR_TRUNC
11271130
// as an alternative.
@@ -1218,8 +1221,8 @@ Expected<action_iterator> GlobalISelEmitter::importExplicitUseRenderer(
12181221
return OpTy.takeError();
12191222

12201223
unsigned TempRegID = Rule.allocateTempRegID();
1221-
InsertPt = Rule.insertAction<MakeTempRegisterAction>(
1222-
InsertPt, *OpTy, TempRegID);
1224+
InsertPt =
1225+
Rule.insertAction<MakeTempRegisterAction>(InsertPt, *OpTy, TempRegID);
12231226
DstMIBuilder.addRenderer<TempRegRenderer>(TempRegID);
12241227

12251228
auto InsertPtOrError = createAndImportSubInstructionRenderer(
@@ -1229,7 +1232,8 @@ Expected<action_iterator> GlobalISelEmitter::importExplicitUseRenderer(
12291232
return InsertPtOrError.get();
12301233
}
12311234

1232-
return failedImport("Dst pattern child isn't a leaf node or an MBB" + llvm::to_string(*DstChild));
1235+
return failedImport("Dst pattern child isn't a leaf node or an MBB" +
1236+
llvm::to_string(*DstChild));
12331237
}
12341238

12351239
// It could be a specific immediate in which case we should just check for
@@ -1324,9 +1328,8 @@ Expected<BuildMIAction &> GlobalISelEmitter::createAndImportInstructionRenderer(
13241328
&Target.getInstruction(RK.getDef("COPY")));
13251329
BuildMIAction &CopyToPhysRegMIBuilder =
13261330
*static_cast<BuildMIAction *>(InsertPt->get());
1327-
CopyToPhysRegMIBuilder.addRenderer<AddRegisterRenderer>(Target,
1328-
PhysInput.first,
1329-
true);
1331+
CopyToPhysRegMIBuilder.addRenderer<AddRegisterRenderer>(
1332+
Target, PhysInput.first, true);
13301333
CopyToPhysRegMIBuilder.addRenderer<CopyPhysRegRenderer>(PhysInput.first);
13311334
}
13321335

@@ -1399,19 +1402,19 @@ GlobalISelEmitter::createAndImportSubInstructionRenderer(
13991402
auto SuperClass = inferRegClassFromPattern(Dst->getChild(0));
14001403
if (!SuperClass)
14011404
return failedImport(
1402-
"Cannot infer register class from EXTRACT_SUBREG operand #0");
1405+
"Cannot infer register class from EXTRACT_SUBREG operand #0");
14031406

14041407
auto SubIdx = inferSubRegIndexForNode(Dst->getChild(1));
14051408
if (!SubIdx)
14061409
return failedImport("EXTRACT_SUBREG child #1 is not a subreg index");
14071410

14081411
const auto SrcRCDstRCPair =
1409-
(*SuperClass)->getMatchingSubClassWithSubRegs(CGRegs, *SubIdx);
1412+
(*SuperClass)->getMatchingSubClassWithSubRegs(CGRegs, *SubIdx);
14101413
assert(SrcRCDstRCPair->second && "Couldn't find a matching subclass");
14111414
M.insertAction<ConstrainOperandToRegClassAction>(
1412-
InsertPt, DstMIBuilder.getInsnID(), 0, *SrcRCDstRCPair->second);
1415+
InsertPt, DstMIBuilder.getInsnID(), 0, *SrcRCDstRCPair->second);
14131416
M.insertAction<ConstrainOperandToRegClassAction>(
1414-
InsertPt, DstMIBuilder.getInsnID(), 1, *SrcRCDstRCPair->first);
1417+
InsertPt, DstMIBuilder.getInsnID(), 1, *SrcRCDstRCPair->first);
14151418

14161419
// We're done with this pattern! It's eligible for GISel emission; return
14171420
// it.
@@ -1424,23 +1427,23 @@ GlobalISelEmitter::createAndImportSubInstructionRenderer(
14241427
auto SubClass = inferRegClassFromPattern(Dst->getChild(1));
14251428
if (!SubClass)
14261429
return failedImport(
1427-
"Cannot infer register class from SUBREG_TO_REG child #1");
1428-
auto SuperClass = inferSuperRegisterClass(Dst->getExtType(0),
1429-
Dst->getChild(2));
1430+
"Cannot infer register class from SUBREG_TO_REG child #1");
1431+
auto SuperClass =
1432+
inferSuperRegisterClass(Dst->getExtType(0), Dst->getChild(2));
14301433
if (!SuperClass)
14311434
return failedImport(
1432-
"Cannot infer register class for SUBREG_TO_REG operand #0");
1435+
"Cannot infer register class for SUBREG_TO_REG operand #0");
14331436
M.insertAction<ConstrainOperandToRegClassAction>(
1434-
InsertPt, DstMIBuilder.getInsnID(), 0, **SuperClass);
1437+
InsertPt, DstMIBuilder.getInsnID(), 0, **SuperClass);
14351438
M.insertAction<ConstrainOperandToRegClassAction>(
1436-
InsertPt, DstMIBuilder.getInsnID(), 2, **SubClass);
1439+
InsertPt, DstMIBuilder.getInsnID(), 2, **SubClass);
14371440
return InsertPtOrError.get();
14381441
}
14391442

14401443
if (OpName == "REG_SEQUENCE") {
14411444
auto SuperClass = inferRegClassFromPattern(Dst->getChild(0));
14421445
M.insertAction<ConstrainOperandToRegClassAction>(
1443-
InsertPt, DstMIBuilder.getInsnID(), 0, **SuperClass);
1446+
InsertPt, DstMIBuilder.getInsnID(), 0, **SuperClass);
14441447

14451448
unsigned Num = Dst->getNumChildren();
14461449
for (unsigned I = 1; I != Num; I += 2) {
@@ -1451,10 +1454,10 @@ GlobalISelEmitter::createAndImportSubInstructionRenderer(
14511454
return failedImport("REG_SEQUENCE child is not a subreg index");
14521455

14531456
const auto SrcRCDstRCPair =
1454-
(*SuperClass)->getMatchingSubClassWithSubRegs(CGRegs, *SubIdx);
1457+
(*SuperClass)->getMatchingSubClassWithSubRegs(CGRegs, *SubIdx);
14551458
assert(SrcRCDstRCPair->second && "Couldn't find a matching subclass");
14561459
M.insertAction<ConstrainOperandToRegClassAction>(
1457-
InsertPt, DstMIBuilder.getInsnID(), I, *SrcRCDstRCPair->second);
1460+
InsertPt, DstMIBuilder.getInsnID(), I, *SrcRCDstRCPair->second);
14581461
}
14591462

14601463
return InsertPtOrError.get();
@@ -1514,7 +1517,7 @@ Expected<action_iterator> GlobalISelEmitter::importExplicitDefRenderers(
15141517

15151518
unsigned TempRegID = M.allocateTempRegID();
15161519
InsertPt =
1517-
M.insertAction<MakeTempRegisterAction>(InsertPt, *OpTy, TempRegID);
1520+
M.insertAction<MakeTempRegisterAction>(InsertPt, *OpTy, TempRegID);
15181521
DstMIBuilder.addRenderer<TempRegRenderer>(TempRegID, true, nullptr, true);
15191522
}
15201523

@@ -1548,11 +1551,11 @@ Expected<action_iterator> GlobalISelEmitter::importExplicitUseRenderers(
15481551
return ExtractSrcTy.takeError();
15491552

15501553
unsigned TempRegID = M.allocateTempRegID();
1551-
InsertPt = M.insertAction<MakeTempRegisterAction>(
1552-
InsertPt, *ExtractSrcTy, TempRegID);
1554+
InsertPt = M.insertAction<MakeTempRegisterAction>(InsertPt, *ExtractSrcTy,
1555+
TempRegID);
15531556

15541557
auto InsertPtOrError = createAndImportSubInstructionRenderer(
1555-
++InsertPt, M, ValChild, Src, TempRegID);
1558+
++InsertPt, M, ValChild, Src, TempRegID);
15561559
if (auto Error = InsertPtOrError.takeError())
15571560
return std::move(Error);
15581561

@@ -1569,7 +1572,7 @@ Expected<action_iterator> GlobalISelEmitter::importExplicitUseRenderers(
15691572
CodeGenRegisterClass *RC = CGRegs.getRegClass(RCDef);
15701573

15711574
const auto SrcRCDstRCPair =
1572-
RC->getMatchingSubClassWithSubRegs(CGRegs, SubIdx);
1575+
RC->getMatchingSubClassWithSubRegs(CGRegs, SubIdx);
15731576
if (SrcRCDstRCPair) {
15741577
assert(SrcRCDstRCPair->second && "Couldn't find a matching subclass");
15751578
if (SrcRCDstRCPair->first != RC)
@@ -1670,8 +1673,8 @@ Expected<action_iterator> GlobalISelEmitter::importExplicitUseRenderers(
16701673

16711674
const CGIOperandList::OperandInfo &DstIOperand = DstI->Operands[InstOpNo];
16721675
DagInit *DefaultOps = DstIOperand.Rec->getValueAsDag("DefaultOps");
1673-
if (auto Error = importDefaultOperandRenderers(
1674-
InsertPt, M, DstMIBuilder, DefaultOps))
1676+
if (auto Error = importDefaultOperandRenderers(InsertPt, M, DstMIBuilder,
1677+
DefaultOps))
16751678
return std::move(Error);
16761679
++NumDefaultOps;
16771680
continue;
@@ -1706,8 +1709,7 @@ Error GlobalISelEmitter::importDefaultOperandRenderers(
17061709
if (const DefInit *DefaultDagOperator =
17071710
dyn_cast<DefInit>(DefaultDagOp->getOperator())) {
17081711
if (DefaultDagOperator->getDef()->isSubClassOf("ValueType")) {
1709-
OpTyOrNone = MVTToLLT(getValueType(
1710-
DefaultDagOperator->getDef()));
1712+
OpTyOrNone = MVTToLLT(getValueType(DefaultDagOperator->getDef()));
17111713
DefaultOp = DefaultDagOp->getArg(0);
17121714
}
17131715
}
@@ -1720,10 +1722,10 @@ Error GlobalISelEmitter::importDefaultOperandRenderers(
17201722
M.insertAction<MakeTempRegisterAction>(InsertPt, *OpTyOrNone,
17211723
TempRegID);
17221724
InsertPt = M.insertAction<BuildMIAction>(
1723-
InsertPt, M.allocateOutputInsnID(),
1724-
&Target.getInstruction(RK.getDef("IMPLICIT_DEF")));
1725-
BuildMIAction &IDMIBuilder = *static_cast<BuildMIAction *>(
1726-
InsertPt->get());
1725+
InsertPt, M.allocateOutputInsnID(),
1726+
&Target.getInstruction(RK.getDef("IMPLICIT_DEF")));
1727+
BuildMIAction &IDMIBuilder =
1728+
*static_cast<BuildMIAction *>(InsertPt->get());
17271729
IDMIBuilder.addRenderer<TempRegRenderer>(TempRegID);
17281730
DstMIBuilder.addRenderer<TempRegRenderer>(TempRegID);
17291731
} else {
@@ -2021,7 +2023,8 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
20212023
} else if (DstIName == "EXTRACT_SUBREG") {
20222024
auto InferredClass = inferRegClassFromPattern(Dst->getChild(0));
20232025
if (!InferredClass)
2024-
return failedImport("Could not infer class for EXTRACT_SUBREG operand #0");
2026+
return failedImport(
2027+
"Could not infer class for EXTRACT_SUBREG operand #0");
20252028

20262029
// We can assume that a subregister is in the same bank as it's super
20272030
// register.
@@ -2103,7 +2106,7 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
21032106
auto SuperClass = inferRegClassFromPattern(Dst->getChild(0));
21042107
if (!SuperClass)
21052108
return failedImport(
2106-
"Cannot infer register class from EXTRACT_SUBREG operand #0");
2109+
"Cannot infer register class from EXTRACT_SUBREG operand #0");
21072110

21082111
auto SubIdx = inferSubRegIndexForNode(Dst->getChild(1));
21092112
if (!SubIdx)
@@ -2116,17 +2119,18 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
21162119
// FIXME: This may introduce an extra copy if the chosen class doesn't
21172120
// actually contain the subregisters.
21182121
assert(Src->getExtTypes().size() == 1 &&
2119-
"Expected Src of EXTRACT_SUBREG to have one result type");
2122+
"Expected Src of EXTRACT_SUBREG to have one result type");
21202123

21212124
const auto SrcRCDstRCPair =
2122-
(*SuperClass)->getMatchingSubClassWithSubRegs(CGRegs, *SubIdx);
2125+
(*SuperClass)->getMatchingSubClassWithSubRegs(CGRegs, *SubIdx);
21232126
if (!SrcRCDstRCPair) {
21242127
return failedImport("subreg index is incompatible "
21252128
"with inferred reg class");
21262129
}
21272130

21282131
assert(SrcRCDstRCPair->second && "Couldn't find a matching subclass");
2129-
M.addAction<ConstrainOperandToRegClassAction>(0, 0, *SrcRCDstRCPair->second);
2132+
M.addAction<ConstrainOperandToRegClassAction>(0, 0,
2133+
*SrcRCDstRCPair->second);
21302134
M.addAction<ConstrainOperandToRegClassAction>(0, 1, *SrcRCDstRCPair->first);
21312135

21322136
// We're done with this pattern! It's eligible for GISel emission; return
@@ -2194,7 +2198,7 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
21942198
return failedImport("REG_SEQUENCE child is not a subreg index");
21952199

21962200
const auto SrcRCDstRCPair =
2197-
(*SuperClass)->getMatchingSubClassWithSubRegs(CGRegs, *SubIdx);
2201+
(*SuperClass)->getMatchingSubClassWithSubRegs(CGRegs, *SubIdx);
21982202

21992203
M.addAction<ConstrainOperandToRegClassAction>(0, I,
22002204
*SrcRCDstRCPair->second);
@@ -2241,8 +2245,8 @@ void GlobalISelEmitter::emitCxxPredicateFns(
22412245
}
22422246

22432247
OS << "bool " << Target.getName() << "InstructionSelector::test" << ArgName
2244-
<< "Predicate_" << TypeIdentifier << "(unsigned PredicateID, " << ArgType << " "
2245-
<< ArgName << AdditionalArgs <<") const {\n"
2248+
<< "Predicate_" << TypeIdentifier << "(unsigned PredicateID, " << ArgType
2249+
<< " " << ArgName << AdditionalArgs << ") const {\n"
22462250
<< AdditionalDeclarations;
22472251
if (!AdditionalDeclarations.empty())
22482252
OS << "\n";
@@ -2346,8 +2350,10 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
23462350
// Track the GINodeEquiv definitions.
23472351
gatherNodeEquivs();
23482352

2349-
emitSourceFileHeader(("Global Instruction Selector for the " +
2350-
Target.getName() + " target").str(), OS);
2353+
emitSourceFileHeader(
2354+
("Global Instruction Selector for the " + Target.getName() + " target")
2355+
.str(),
2356+
OS);
23512357
std::vector<RuleMatcher> Rules;
23522358
// Look through the SelectionDAG patterns we found, possibly emitting some.
23532359
for (const PatternToMatch &Pat : CGP.ptms()) {
@@ -2465,15 +2471,17 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
24652471
});
24662472

24672473
SubtargetFeatureInfo::emitComputeAvailableFeatures(
2468-
Target.getName(), "InstructionSelector", "computeAvailableModuleFeatures",
2474+
Target.getName(), "InstructionSelector", "computeAvailableModuleFeatures",
24692475
ModuleFeatures, OS);
24702476

2471-
2472-
OS << "void " << Target.getName() << "InstructionSelector"
2473-
"::setupGeneratedPerFunctionState(MachineFunction &MF) {\n"
2474-
" AvailableFunctionFeatures = computeAvailableFunctionFeatures("
2475-
"(const " << Target.getName() << "Subtarget *)&MF.getSubtarget(), &MF);\n"
2476-
"}\n";
2477+
OS << "void " << Target.getName()
2478+
<< "InstructionSelector"
2479+
"::setupGeneratedPerFunctionState(MachineFunction &MF) {\n"
2480+
" AvailableFunctionFeatures = computeAvailableFunctionFeatures("
2481+
"(const "
2482+
<< Target.getName()
2483+
<< "Subtarget *)&MF.getSubtarget(), &MF);\n"
2484+
"}\n";
24772485

24782486
SubtargetFeatureInfo::emitComputeAvailableFeatures(
24792487
Target.getName(), "InstructionSelector",

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